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RFC: [AMDGPU] Select CONVERGENCECTRL_GLUE generically #87509

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RFC: [AMDGPU] Select CONVERGENCECTRL_GLUE generically #87509

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1 change: 1 addition & 0 deletions llvm/include/llvm/CodeGen/SelectionDAGISel.h
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Original file line number Diff line number Diff line change
Expand Up @@ -462,6 +462,7 @@ class SelectionDAGISel : public MachineFunctionPass {
void Select_CONVERGENCECTRL_ANCHOR(SDNode *N);
void Select_CONVERGENCECTRL_ENTRY(SDNode *N);
void Select_CONVERGENCECTRL_LOOP(SDNode *N);
void Select_CONVERGENCECTRL_GLUE(SDNode *N);

void pushStackMapLiveVariable(SmallVectorImpl<SDValue> &Ops, SDValue Operand,
SDLoc DL);
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2 changes: 1 addition & 1 deletion llvm/include/llvm/IR/IntrinsicsAMDGPU.td
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Expand Up @@ -2175,7 +2175,7 @@ def int_amdgcn_wave_reduce_umax : AMDGPUWaveReduce;
def int_amdgcn_readfirstlane :
ClangBuiltin<"__builtin_amdgcn_readfirstlane">,
Intrinsic<[llvm_i32_ty], [llvm_i32_ty],
[IntrNoMem, IntrConvergent, IntrWillReturn, IntrNoCallback, IntrNoFree]>;
[IntrNoMem, IntrConvergent, IntrWillReturn, IntrNoCallback, IntrNoFree], "", [SDNPOptInGlue]>;

// The lane argument must be uniform across the currently active threads of the
// current wave. Otherwise, the result is undefined.
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8 changes: 8 additions & 0 deletions llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
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Expand Up @@ -2385,6 +2385,11 @@ void SelectionDAGISel::Select_CONVERGENCECTRL_LOOP(SDNode *N) {
N->getValueType(0), N->getOperand(0));
}

void SelectionDAGISel::Select_CONVERGENCECTRL_GLUE(SDNode *N) {
CurDAG->SelectNodeTo(N, TargetOpcode::CONVERGENCECTRL_GLUE,
N->getValueType(0), N->getOperand(0));
}

void SelectionDAGISel::pushStackMapLiveVariable(SmallVectorImpl<SDValue> &Ops,
SDValue OpVal, SDLoc DL) {
SDNode *OpNode = OpVal.getNode();
Expand Down Expand Up @@ -3141,6 +3146,9 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch,
case ISD::CONVERGENCECTRL_LOOP:
Select_CONVERGENCECTRL_LOOP(NodeToMatch);
return;
case ISD::CONVERGENCECTRL_GLUE:
Select_CONVERGENCECTRL_GLUE(NodeToMatch);
return;
}

assert(!NodeToMatch->isMachineOpcode() && "Node already selected!");
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27 changes: 4 additions & 23 deletions llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
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Expand Up @@ -2688,18 +2688,7 @@ void AMDGPUDAGToDAGISel::SelectINTRINSIC_W_CHAIN(SDNode *N) {

void AMDGPUDAGToDAGISel::SelectINTRINSIC_WO_CHAIN(SDNode *N) {
unsigned IntrID = N->getConstantOperandVal(0);
unsigned Opcode = AMDGPU::INSTRUCTION_LIST_END;
SDNode *ConvGlueNode = N->getGluedNode();
if (ConvGlueNode) {
// FIXME: Possibly iterate over multiple glue nodes?
assert(ConvGlueNode->getOpcode() == ISD::CONVERGENCECTRL_GLUE);
ConvGlueNode = ConvGlueNode->getOperand(0).getNode();
ConvGlueNode =
CurDAG->getMachineNode(TargetOpcode::CONVERGENCECTRL_GLUE, {},
MVT::Glue, SDValue(ConvGlueNode, 0));
} else {
ConvGlueNode = nullptr;
}
unsigned Opcode;
switch (IntrID) {
case Intrinsic::amdgcn_wqm:
Opcode = AMDGPU::WQM;
Expand Down Expand Up @@ -2731,19 +2720,11 @@ void AMDGPUDAGToDAGISel::SelectINTRINSIC_WO_CHAIN(SDNode *N) {
break;
default:
SelectCode(N);
break;
}

if (Opcode != AMDGPU::INSTRUCTION_LIST_END) {
SDValue Src = N->getOperand(1);
CurDAG->SelectNodeTo(N, Opcode, N->getVTList(), {Src});
return;
}

if (ConvGlueNode) {
SmallVector<SDValue, 4> NewOps(N->op_begin(), N->op_end());
NewOps.push_back(SDValue(ConvGlueNode, 0));
CurDAG->MorphNodeTo(N, N->getOpcode(), N->getVTList(), NewOps);
}
SDValue Src = N->getOperand(1);
CurDAG->SelectNodeTo(N, Opcode, N->getVTList(), {Src});
}

void AMDGPUDAGToDAGISel::SelectINTRINSIC_VOID(SDNode *N) {
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