[RISCV] Only allow up to e64 in vsetvli

[palmer-dabbelt]

These larger SEWs aren't in the ratified V spec. Thanks to dzaima and sorear on IRC for pointing this one out.

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[llvmbot]

@llvm/pr-subscribers-mc

@llvm/pr-subscribers-backend-risc-v

Author: Palmer Dabbelt (palmer-dabbelt)

Changes

These larger SEWs aren't in the ratified V spec. Thanks to dzaima and sorear on IRC for pointing this one out.

---

Full diff: https://github.com/llvm/llvm-project/pull/92010.diff

2 Files Affected:

• (modified) llvm/include/llvm/TargetParser/RISCVTargetParser.h (+1-1)
• (modified) llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp (+1-1)

diff --git a/llvm/include/llvm/TargetParser/RISCVTargetParser.h b/llvm/include/llvm/TargetParser/RISCVTargetParser.h
index cdd19189f8dc7..5b1494efe7bdc 100644
--- a/llvm/include/llvm/TargetParser/RISCVTargetParser.h
+++ b/llvm/include/llvm/TargetParser/RISCVTargetParser.h
@@ -61,7 +61,7 @@ enum {
 namespace RISCVVType {
 // Is this a SEW value that can be encoded into the VTYPE format.
 inline static bool isValidSEW(unsigned SEW) {
-  return isPowerOf2_32(SEW) && SEW >= 8 && SEW <= 1024;
+  return isPowerOf2_32(SEW) && SEW >= 8 && SEW <= 64;
 }
 
 // Is this a LMUL value that can be encoded into the VTYPE format.
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index 123b37442329f..6bdd038bd07e9 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -2227,7 +2227,7 @@ bool RISCVAsmParser::generateVTypeError(SMLoc ErrorLoc) {
   return Error(
       ErrorLoc,
       "operand must be "
-      "e[8|16|32|64|128|256|512|1024],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]");
+      "e[8|16|32|64],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]");
 }
 
 ParseStatus RISCVAsmParser::parseMaskReg(OperandVector &Operands) {

[jrtc27]

66da87d is the commit that first introduced this check which was committed just after V 0.9 (haven't checked if it implemented 0.9 or stuck with 0.8), and up until 1.0 64 < SEW <= 1024 was reserved (see riscvarchive/riscv-v-spec@c32b714).

[topperc]

Can you add tests to test/MC/RISCV/rvv/invalid.s? I see a test for e2048 in there. I guess we didn't have any tests for e128-e1024.

[palmer-dabbelt]

Can you add tests to test/MC/RISCV/rvv/invalid.s? I see a test for e2048 in there. I guess we didn't have any tests for e128-e1024.

Done. Also I fixed up the errors in those tests (I'm no building/testing this locally, I figured some CI would do it for me).

[topperc]

LGTM

[topperc]

@palmer-dabbelt I assume you need someone to commit this?

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