Repository navigation
What's Changed
This is NOT a long-term support version!!!
It is my great pleasure to announce the v1.3.0 release of OpenFPGA! 🚀
It has been four years since our last release, v1.1.541. During this period, driven by the growing demand from industry for FPGA tapeouts, OpenFPGA has undergone intensive development, with new contributions and pull requests arriving almost every day!
This release brings a wealth of technical improvements.
- Support VTR latest (version >9) as submodule
- Support Yosys as API-level integration
- Support little-endian in netlist generation
- Support systemverilog
- Support MacOS, Windows
- Memory initialization support
- Support gz in netlist and bitstream outputs
- Physical equivalent sites support
- Support different I/O capacity on perimeters
- Support multi-column and multi-row heterogeneous blocks
- Support L-shape FPGA fabric
- Support different routing channel width and wire distribution in X- and Y- direction
- Custom unused routing multiplexer configuration
- Support single-stage routing
- Support group tiles
- Support group configuration memory blocks
- Support exact placement of primitive blocks
- Support bus-based local routing
- Off-fabric timing annotation
- Customization on last stage MUX cells
- Custom PCF commands
- Enhancements on direction conections
- Support custom fpga top-level wrappers
- Support don't care mode bits
- Support HEX format in mode bits
- Support multiple clocks on configuration chains
- Support Enhanced Connection Block (ECB)
- Programmable clock network (including reset)
- Support bus-based local routing
- Support flexible direction connections
- Support flexible I/O block architecture (registers etc.)
- Support calling shell command in OpenFPGA shell
- Support to load OpenFPGA as a dynamic library for Tcl integration
- OpenFPGA shell supports command auto-completion
- OpenFPGA shell can accept stringstream for commands to be executed (option '-x')
New Contributors
🙏 A huge thank-you to all our contributors!
Your dedication, technical expertise, and continuous support have made this release possible. Open-source projects thrive because of communities like ours, and I am grateful to everyone who has contributed to OpenFPGA.
- @mustafaarslan0 made their first contribution in #835
- @yunuseryilmaz18 made their first contribution in #839
- @scott-temple made their first contribution in #1050
- @chungshien made their first contribution in #1252
- @KyleChuang made their first contribution in #1312
- @treelin611 made their first contribution in #1467
- @victorzh001 made their first contribution in #1583
- @rafljiarui made their first contribution in #1822
- @fkosar-ql made their first contribution in #1866
- @ruck314 made their first contribution in #2122
- @amin1377 made their first contribution in #2173
- @lalit-quicklogic made their first contribution in #2467
- @oscarcheng105 made their first contribution in #2446
- @tmarhguy made their first contribution in #2683
Full Changelog: v1.1.525...v1.3.0