[fpga] Add AES SCA trigger delay

Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org>

Author: nasahlpa

hw/top_earlgrey/rtl/autogen/chip_earlgrey_cw310.sv

@@ -1061,7 +1061,7 @@ module chip_earlgrey_cw310 #(
   top_earlgrey #(
     .SecAesMasking(1'b1),
     .SecAesSBoxImpl(aes_pkg::SBoxImplDom),
-    .SecAesStartTriggerDelay(0),
+    .SecAesStartTriggerDelay(320),
     .SecAesAllowForcingMasks(1'b1),
     .CsrngSBoxImpl(aes_pkg::SBoxImplLut),
     .OtbnRegFile(otbn_pkg::RegFileFPGA),

hw/top_earlgrey/templates/chiplevel.sv.tpl

@@ -1138,7 +1138,7 @@ module chip_${top["name"]}_${target["name"]} #(
 % if target["name"] in ["cw310", "cw340"]:
     .SecAesMasking(1'b1),
     .SecAesSBoxImpl(aes_pkg::SBoxImplDom),
-    .SecAesStartTriggerDelay(0),
+    .SecAesStartTriggerDelay(320),
     .SecAesAllowForcingMasks(1'b1),
     .CsrngSBoxImpl(aes_pkg::SBoxImplLut),
     .OtbnRegFile(otbn_pkg::RegFileFPGA),