Work around Migen's finalization being subtly order dependent

[whitequark]

Right now, in Migen, if the module tree looks like this:

top
\---- probe
\---- microscope

and finalizing microscope makes the module tree look like this:

top
\---- probe ----- ps_arm
\---- microscope

whether any Verilog will actually be generated for ps_arm is
dependent on traversal order of submodules, which cannot be
relied upon. This causes microscope /dev/ttyX singles to hang.

Avoid this by making finalization of probes order-independent.

@sbourdeauducq Not only this broke microscope in a nasty way, but this is one of the worst footguns in Migen that I've hit constantly in Glasgow... I think something should be done about it.

[sbourdeauducq]

It's a migen bug, if a finalize function creates a submodule, then Verilog should always be emitted for that submodule.

[whitequark]

Are you opposed to merging this in meantime? I feel like it makes the logic in microscope more straightforward, too.

[sbourdeauducq]

What about this in Insert:

def do_finalize(self):
    if self.registry.is_enabled(self):
        self.create_insert_logic()

[whitequark]

Done