Verilog-HDL

This repo contains some basic hardware and logic designs and their respective testbenches written in Verilog HDL

Name		Name	Last commit message	Last commit date
Latest commit History 4 Commits
CNN		CNN
neuron		neuron
README.md		README.md
and_gt.v		and_gt.v
and_tb.v		and_tb.v
array_ex.v		array_ex.v
array_ex_tb.v		array_ex_tb.v
array_test.v		array_test.v
counter4_down.v		counter4_down.v
counter4_down_tb.v		counter4_down_tb.v
counter4_up.v		counter4_up.v
counter4_up_tb.v		counter4_up_tb.v
dff.v		dff.v
dff_5hz.v		dff_5hz.v
dff_5hz_tb.v		dff_5hz_tb.v
dflop.v		dflop.v
dflop_tb.v		dflop_tb.v
example1.v		example1.v
fa.v		fa.v
ha.v		ha.v
halfSubtractor.v		halfSubtractor.v
halfSubtractor_tb.v		halfSubtractor_tb.v
hello.v		hello.v
hello_tb.v		hello_tb.v
jk_ff_race.v		jk_ff_race.v
jk_ff_race_tb.v		jk_ff_race_tb.v
jk_flop.v		jk_flop.v
jk_flop_tb.v		jk_flop_tb.v
maxPooling.v		maxPooling.v
maxPooling_tb.v		maxPooling_tb.v
mem16.v		mem16.v
mem16_tb.v		mem16_tb.v
mod_counter.v		mod_counter.v
mod_counter_tb.v		mod_counter_tb.v
mux.v		mux.v
mux_tb.v		mux_tb.v
ring_counter.v		ring_counter.v
ring_counter_tb.v		ring_counter_tb.v
ripple_counter.v		ripple_counter.v
ripple_counter_tb.v		ripple_counter_tb.v
shift_reg.v		shift_reg.v
shift_reg_tb.v		shift_reg_tb.v
test_tb.v		test_tb.v
tflop.v		tflop.v
tflop_tb.v		tflop_tb.v
upDown_counter.v		upDown_counter.v
upDown_counter_tb.v		upDown_counter_tb.v
vending_machine.v		vending_machine.v
vending_machine_tb.v		vending_machine_tb.v

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