Updating submodules.

 * litedram changed from ea1ac4d to 5820970
    * 5820970 - frontend/crossbar: fix timvideos#49 <Florent Kermarrec>
    * 5fb8afe - frontend/axi: omit bank in rdata connect <Florent Kermarrec>
    *   06ca53d - Merge pull request timvideos#48 from enjoy-digital/staging <enjoy-digital>
    |\
    | *   5a4d063 - Merge branch 'master' into staging <enjoy-digital>
    | |\
    | |/
    |/|
    * | 5984eaa - core: change api for out-of-order. (with_reordering passed to controller and not ports). <Florent Kermarrec>
    * | 6e10dae - core/bankmachine/write to precharge: indicate that AL=0 <Florent Kermarrec>
    * |   869c8ee - Merge pull request timvideos#46 from enjoy-digital/WritePrechargeFix <enjoy-digital>
    |\ \
    | * | 0405f41 - Update the write-to-precharge timings so it works with 1:2 <>
    * | | 30c32f5 - example/litedram_gen: simplify clocking with new S7PLL module, a lot easier :) <Florent Kermarrec>
    |/ /
    * | 2a3cacb - core/bankmachine: minor cleanup on trc/tras <Florent Kermarrec>
    * |   42ccf05 - Merge pull request timvideos#45 from enjoy-digital/tRAS_FIX <enjoy-digital>
    |\ \
    | * | 79b1421 - Auto precharge is too pessimistic, it will wait on its own for a valid time to execute <John Sully>
    | * | 177d739 - Implement tRAS <John Sully>
    * | |   5902027 - Merge pull request timvideos#44 from enjoy-digital/tRC_Fix <enjoy-digital>
    |\ \ \
    | |/ /
    | * | 5f6b857 - This adds support for tRC timing parameters <John Sully>
    |/ /
    * |   1777720 - Merge pull request timvideos#42 from enjoy-digital/HalfRateSequentialFix <enjoy-digital>
    |\ \
    | * | 06c8c2a - The actual fix <John Sully>
    | * | e22580f - remove unnecessary file <John Sully>
    | * | c028786 - Fix overflow bug from code review <John Sully>
    | * | 8447d69 - We wait an extra cycle for no reason <John Sully>
    |/ /
    | *   04aa04d - Merge pull request timvideos#43 from enjoy-digital/EfficencyFixes <enjoy-digital>
    | |\
    |/ /
    | * c4bd842 - Fix many bugs <John Sully>
    | * fa0f3b2 - Use the ready signal for cas_allowed so that arbitrators know not to iterate <John Sully>
    |/
    * c12404e - README: Add ECC <Florent Kermarrec>
    * 3f4c14b - frontend/ecc: expose incident bits, change clear register name <Florent Kermarrec>
    * b9aadf1 - frontend/axi: remove write buffer reservation (not needed) <Florent Kermarrec>

 * liteeth changed from 3d86844 to 40b99ec
    * 40b99ec - test: use new RemoteClient import <Florent Kermarrec>
    * c370e9f - phy/model: remove creation/deletion of ethernet tap (now handled by the simulator) <Florent Kermarrec>

 * litepcie changed from 3e8de2d to a09d225
    * a09d225 - test: use new RemoteClient import <Florent Kermarrec>

 * litesata changed from fb72044 to b78a731
    * b78a731 - test: use new RemoteClient import <Florent Kermarrec>

 * litescope changed from 686db4f to 1634fa3
    * 1634fa3 - test: use new RemoteClient import <Florent Kermarrec>
    * cb27987 - examples/make: look for platform in migen if not present in litex <Florent Kermarrec>

 * litex changed from v0.1-451-g537b0e90 to v0.1-492-g934a5da5
    * 934a5da5 - soc/cores/clock: add expose_drp on S7PLL/S7MMCM <Florent Kermarrec>
    *   9097573e - Merge pull request timvideos#109 from cr1901/xip-improve <enjoy-digital>
    |\
    | * 0ff6d586 - Distinguish crt0 variants more clearly, update BIOS to use CTR variant (as it has no .data section). <William D. Jones>
    | * 81060081 - integration/builder: Create EXECUTE_IN_PLACE Makefile variable to complement COPY_TO_MAIN_RAM. <William D. Jones>
    | * db906190 - integration/builder: Add LiteX define to generated variables (to distinguish MiSoC and LiteX). <William D. Jones>
    * | 082b0301 - targets: use new clock abstraction on all 7-series targets <Florent Kermarrec>
    * | 74e74dc0 - soc/cores/clock: different clkin_freq_range for pll and mmcm <Florent Kermarrec>
    * | 91d8cc2d - soc/cores/clock: different vco_freq_range for pll and mmcm <Florent Kermarrec>
    * | 6cd95494 - soc/core/clock: allow selecting buffer type (None, BUFG, BUFR). (default = BUFG) <Florent Kermarrec>
    * | 912ca323 - soc/cores/clock: create specific S7IDELAYCTRL module <Florent Kermarrec>
    * | baec87f5 - soc/cores/clock: add S7MMCM support <Florent Kermarrec>
    * | ef405249 - soc/cores/clocks/S7PLL: add speedgrade support, default to -1 (slowest) <Florent Kermarrec>
    * | 5415b521 - targets/arty: use new clock abstraction module (compile, untested on board) <Florent Kermarrec>
    * | 63fc3950 - soc/cores: init clock abstraction module <Florent Kermarrec>
    |/
    * 70a32ed8 - sim/verilator: add multithread support (default=1) <Florent Kermarrec>
    * 7f0d116d - soc_core: use cpu instead of cpu_or_bridge internally (keep retro-compat for now) <Florent Kermarrec>
    * 22febe95 - boards/targets: uniformize things between targets <Florent Kermarrec>
    * 01b025aa - soc_core/get_mem_data: add endianness support and use it in builder/initialize_rom to avoid duplication <Florent Kermarrec>
    * b528a005 - cores/cpu: add software informations to cpu and simplify cpu_interface <Florent Kermarrec>
    * 2d785cb0 - boards/plarforms: fix issues found while testing simple design on all platforms <Florent Kermarrec>
    * 0b0e3ac1 - test/test_targets: test simple design with all platforms <Florent Kermarrec>
    * c88029d3 - soc_core: add uart-stub argument <Florent Kermarrec>
    * 0d2d3959 - setup.py: add litex_simple exec (to ease building simple design) <Florent Kermarrec>
    * e04530e0 - test/test_targets: update and reorganize targets <Florent Kermarrec>
    * e9ed7370 - ease RemoteClient import <Florent Kermarrec>
    *   346dcf94 - Merge pull request timvideos#108 from xobs/use-csr-accessors <enjoy-digital>
    |\
    | * 6f25a0d8 - csr: use external csr_readl()/csr_writel() if present <Sean Cross>
    | * 9a252e36 - csr: use readl()/writel() accessors for accessing mmio <Sean Cross>
    * |   1c1d87f8 - Merge pull request timvideos#106 from cr1901/data-crt0 <Tim Ansell>
    |\ \
    | |/
    | * 9d4da737 - libbase/crt0-lm32.S: Add provisions for loading .data from flash. <William D. Jones>
    |/
    * 01ae7d42 - README: add migen/litex clarification <Florent Kermarrec>
    * 15e584d8 - targets/sim: generate analyzer.csv <Florent Kermarrec>
    * cde72603 - targets/sim: generate csr.csv <Florent Kermarrec>
    * f62df502 - targets/sim: add rom-init <Florent Kermarrec>
    * 1dbf591e - targets/sim: add ram-init param to allow initializing ram from file (faster than tftp) <Florent Kermarrec>
    * 9893c246 - integration/soc_core: add get_mem_data function to read memory content from file <Florent Kermarrec>
    * a3eb2e40 - soc/intergration/builder: fix when no sdram <Florent Kermarrec>
    * 934b08ed - targets/sim: merge in a single class and ease configuration <Florent Kermarrec>
    * bd42b188 - Merge branch 'master' of http://github.com/enjoy-digital/litex <Florent Kermarrec>
    * 3e77ae78 - targets: replace MiniSoC with EthernetSoC <Florent Kermarrec>
    * badd9924 - targets/sim: add EtherboneSoC target (allow accessing wishbone over in simulation with litex_server) <Florent Kermarrec>

 * migen changed from 0.6.dev-168-gca0df1c to 0.6.dev-172-g56f359d
    * 56f359d - Added icebreaker platform. (timvideos#135) <Piotr Esden-Tempski>
    * 88e72a5 - Sayma RTM: expose clock mezzanine gpio as a connector (timvideos#134) <hartytp>
    * 1d3433e - Revert "Emit `default_nettype none." <Sebastien Bourdeauducq>
    * 4621abc - sayma rtm: add clock mezzanine GPIO (timvideos#133) <hartytp>

Full submodule status
--
 5eeb151a748788666534d6ea3da07f90400d24c2 edid-decode (remotes/origin/HEAD)
 a628956da7dc794e6e3c95b31ff9ce3af58bc763 flash_proxies (remotes/origin/HEAD)
 58209708e74999c567389fc514c40acfd739d0a6 litedram (remotes/origin/HEAD)
 40b99ecc05ee490d77477cba542db6d63333c390 liteeth (remotes/origin/HEAD)
 a09d225aafbf98b36913e10366f64ccfad3304af litepcie (remotes/origin/HEAD)
 b78a73110c0c26cf21bf1410329bf1e78286e929 litesata (remotes/origin/HEAD)
 1634fa35bb9f2717ab355ca2e494e1d02fd489ec litescope (remotes/origin/HEAD)
 0a9110f901182a1233cc4e64b6e39175f6784621 liteusb (remotes/origin/HEAD)
 13d85a1fe360678bebd57c55f1b35988c655ae95 litevideo (remotes/origin/HEAD)
 934a5da559a591f92f592dcd3d1bb676218f9796 litex (v0.1-492-g934a5da5)
 56f359d6dc5fff01b36796c8667dd4b58c0428c9 migen (0.6.dev-172-g56f359d)