or1k bios is too large to fit in ROM region #43

mithro · 2018-08-28T05:38:00Z

/home/travis/build/timvideos/HDMI2USB-litex-firmware/third_party/litex/litex/soc/software/bios/sdram.c:353:13: warning: 'read_bitslip' defined but not used [-Wunused-function]
 static void read_bitslip(int *delay, int *high_skew)
             ^
 CC       main.o
 CC       boot-helper-or1k.o
 CC       boot.o
 LD       bios.elf
or1k-elf-ld: bios.elf section `.rodata' will not fit in region `rom'
or1k-elf-ld: region `rom' overflowed by 1516 bytes
make[1]: *** [bios.elf] Error 1

The text was updated successfully, but these errors were encountered:

mithro · 2018-08-28T05:40:13Z

https://travis-ci.org/timvideos/HDMI2USB-litex-firmware/jobs/421351126

Travis CI - Test and Deploy Your Code with Confidence

Means the larger BIOS size on or1k should be understood by `mkimage.py` command. Fixes timvideos#43.

ray-bot · 2018-09-08T18:28:23Z

Hey, Your issue has been resolved 🎉, Thanks!

* litedram changed from ea1ac4d to 5820970 * 5820970 - frontend/crossbar: fix timvideos#49 <Florent Kermarrec> * 5fb8afe - frontend/axi: omit bank in rdata connect <Florent Kermarrec> * 06ca53d - Merge pull request timvideos#48 from enjoy-digital/staging <enjoy-digital> |\ | * 5a4d063 - Merge branch 'master' into staging <enjoy-digital> | |\ | |/ |/| * | 5984eaa - core: change api for out-of-order. (with_reordering passed to controller and not ports). <Florent Kermarrec> * | 6e10dae - core/bankmachine/write to precharge: indicate that AL=0 <Florent Kermarrec> * | 869c8ee - Merge pull request timvideos#46 from enjoy-digital/WritePrechargeFix <enjoy-digital> |\ \ | * | 0405f41 - Update the write-to-precharge timings so it works with 1:2 <> * | | 30c32f5 - example/litedram_gen: simplify clocking with new S7PLL module, a lot easier :) <Florent Kermarrec> |/ / * | 2a3cacb - core/bankmachine: minor cleanup on trc/tras <Florent Kermarrec> * | 42ccf05 - Merge pull request timvideos#45 from enjoy-digital/tRAS_FIX <enjoy-digital> |\ \ | * | 79b1421 - Auto precharge is too pessimistic, it will wait on its own for a valid time to execute <John Sully> | * | 177d739 - Implement tRAS <John Sully> * | | 5902027 - Merge pull request timvideos#44 from enjoy-digital/tRC_Fix <enjoy-digital> |\ \ \ | |/ / | * | 5f6b857 - This adds support for tRC timing parameters <John Sully> |/ / * | 1777720 - Merge pull request timvideos#42 from enjoy-digital/HalfRateSequentialFix <enjoy-digital> |\ \ | * | 06c8c2a - The actual fix <John Sully> | * | e22580f - remove unnecessary file <John Sully> | * | c028786 - Fix overflow bug from code review <John Sully> | * | 8447d69 - We wait an extra cycle for no reason <John Sully> |/ / | * 04aa04d - Merge pull request timvideos#43 from enjoy-digital/EfficencyFixes <enjoy-digital> | |\ |/ / | * c4bd842 - Fix many bugs <John Sully> | * fa0f3b2 - Use the ready signal for cas_allowed so that arbitrators know not to iterate <John Sully> |/ * c12404e - README: Add ECC <Florent Kermarrec> * 3f4c14b - frontend/ecc: expose incident bits, change clear register name <Florent Kermarrec> * b9aadf1 - frontend/axi: remove write buffer reservation (not needed) <Florent Kermarrec> * liteeth changed from 3d86844 to 40b99ec * 40b99ec - test: use new RemoteClient import <Florent Kermarrec> * c370e9f - phy/model: remove creation/deletion of ethernet tap (now handled by the simulator) <Florent Kermarrec> * litepcie changed from 3e8de2d to a09d225 * a09d225 - test: use new RemoteClient import <Florent Kermarrec> * litesata changed from fb72044 to b78a731 * b78a731 - test: use new RemoteClient import <Florent Kermarrec> * litescope changed from 686db4f to 1634fa3 * 1634fa3 - test: use new RemoteClient import <Florent Kermarrec> * cb27987 - examples/make: look for platform in migen if not present in litex <Florent Kermarrec> * litex changed from v0.1-451-g537b0e90 to v0.1-492-g934a5da5 * 934a5da5 - soc/cores/clock: add expose_drp on S7PLL/S7MMCM <Florent Kermarrec> * 9097573e - Merge pull request timvideos#109 from cr1901/xip-improve <enjoy-digital> |\ | * 0ff6d586 - Distinguish crt0 variants more clearly, update BIOS to use CTR variant (as it has no .data section). <William D. Jones> | * 81060081 - integration/builder: Create EXECUTE_IN_PLACE Makefile variable to complement COPY_TO_MAIN_RAM. <William D. Jones> | * db906190 - integration/builder: Add LiteX define to generated variables (to distinguish MiSoC and LiteX). <William D. Jones> * | 082b0301 - targets: use new clock abstraction on all 7-series targets <Florent Kermarrec> * | 74e74dc0 - soc/cores/clock: different clkin_freq_range for pll and mmcm <Florent Kermarrec> * | 91d8cc2d - soc/cores/clock: different vco_freq_range for pll and mmcm <Florent Kermarrec> * | 6cd95494 - soc/core/clock: allow selecting buffer type (None, BUFG, BUFR). (default = BUFG) <Florent Kermarrec> * | 912ca323 - soc/cores/clock: create specific S7IDELAYCTRL module <Florent Kermarrec> * | baec87f5 - soc/cores/clock: add S7MMCM support <Florent Kermarrec> * | ef405249 - soc/cores/clocks/S7PLL: add speedgrade support, default to -1 (slowest) <Florent Kermarrec> * | 5415b521 - targets/arty: use new clock abstraction module (compile, untested on board) <Florent Kermarrec> * | 63fc3950 - soc/cores: init clock abstraction module <Florent Kermarrec> |/ * 70a32ed8 - sim/verilator: add multithread support (default=1) <Florent Kermarrec> * 7f0d116d - soc_core: use cpu instead of cpu_or_bridge internally (keep retro-compat for now) <Florent Kermarrec> * 22febe95 - boards/targets: uniformize things between targets <Florent Kermarrec> * 01b025aa - soc_core/get_mem_data: add endianness support and use it in builder/initialize_rom to avoid duplication <Florent Kermarrec> * b528a005 - cores/cpu: add software informations to cpu and simplify cpu_interface <Florent Kermarrec> * 2d785cb0 - boards/plarforms: fix issues found while testing simple design on all platforms <Florent Kermarrec> * 0b0e3ac1 - test/test_targets: test simple design with all platforms <Florent Kermarrec> * c88029d3 - soc_core: add uart-stub argument <Florent Kermarrec> * 0d2d3959 - setup.py: add litex_simple exec (to ease building simple design) <Florent Kermarrec> * e04530e0 - test/test_targets: update and reorganize targets <Florent Kermarrec> * e9ed7370 - ease RemoteClient import <Florent Kermarrec> * 346dcf94 - Merge pull request timvideos#108 from xobs/use-csr-accessors <enjoy-digital> |\ | * 6f25a0d8 - csr: use external csr_readl()/csr_writel() if present <Sean Cross> | * 9a252e36 - csr: use readl()/writel() accessors for accessing mmio <Sean Cross> * | 1c1d87f8 - Merge pull request timvideos#106 from cr1901/data-crt0 <Tim Ansell> |\ \ | |/ | * 9d4da737 - libbase/crt0-lm32.S: Add provisions for loading .data from flash. <William D. Jones> |/ * 01ae7d42 - README: add migen/litex clarification <Florent Kermarrec> * 15e584d8 - targets/sim: generate analyzer.csv <Florent Kermarrec> * cde72603 - targets/sim: generate csr.csv <Florent Kermarrec> * f62df502 - targets/sim: add rom-init <Florent Kermarrec> * 1dbf591e - targets/sim: add ram-init param to allow initializing ram from file (faster than tftp) <Florent Kermarrec> * 9893c246 - integration/soc_core: add get_mem_data function to read memory content from file <Florent Kermarrec> * a3eb2e40 - soc/intergration/builder: fix when no sdram <Florent Kermarrec> * 934b08ed - targets/sim: merge in a single class and ease configuration <Florent Kermarrec> * bd42b188 - Merge branch 'master' of http://github.com/enjoy-digital/litex <Florent Kermarrec> * 3e77ae78 - targets: replace MiniSoC with EthernetSoC <Florent Kermarrec> * badd9924 - targets/sim: add EtherboneSoC target (allow accessing wishbone over in simulation with litex_server) <Florent Kermarrec> * migen changed from 0.6.dev-168-gca0df1c to 0.6.dev-172-g56f359d * 56f359d - Added icebreaker platform. (timvideos#135) <Piotr Esden-Tempski> * 88e72a5 - Sayma RTM: expose clock mezzanine gpio as a connector (timvideos#134) <hartytp> * 1d3433e - Revert "Emit `default_nettype none." <Sebastien Bourdeauducq> * 4621abc - sayma rtm: add clock mezzanine GPIO (timvideos#133) <hartytp> Full submodule status -- 5eeb151a748788666534d6ea3da07f90400d24c2 edid-decode (remotes/origin/HEAD) a628956da7dc794e6e3c95b31ff9ce3af58bc763 flash_proxies (remotes/origin/HEAD) 58209708e74999c567389fc514c40acfd739d0a6 litedram (remotes/origin/HEAD) 40b99ecc05ee490d77477cba542db6d63333c390 liteeth (remotes/origin/HEAD) a09d225aafbf98b36913e10366f64ccfad3304af litepcie (remotes/origin/HEAD) b78a73110c0c26cf21bf1410329bf1e78286e929 litesata (remotes/origin/HEAD) 1634fa35bb9f2717ab355ca2e494e1d02fd489ec litescope (remotes/origin/HEAD) 0a9110f901182a1233cc4e64b6e39175f6784621 liteusb (remotes/origin/HEAD) 13d85a1fe360678bebd57c55f1b35988c655ae95 litevideo (remotes/origin/HEAD) 934a5da559a591f92f592dcd3d1bb676218f9796 litex (v0.1-492-g934a5da5) 56f359d6dc5fff01b36796c8667dd4b58c0428c9 migen (0.6.dev-172-g56f359d)

* litedram changed from ea1ac4d to 41a8a24 * 41a8a24 - modules: express tFAW in ns <Florent Kermarrec> * 7062068 - modules: split DDR3 in 2 categories: Chips and SO-DIMMs <Florent Kermarrec> * 0f46dc4 - modules: add DDR3-800 timings for MT41J128M16 and use it on arty example <Florent Kermarrec> * 426ae23 - examples/litedram_gen: add sdram_module_speedgrade parameter <Florent Kermarrec> * 1bc016c - test: add test_examples <Florent Kermarrec> * f7f8169 - test: update downconverter/upconverter <Florent Kermarrec> * 8de1d91 - core: add with_bank paramteter to NativePort (cause issues on adaptation is bank is always exposed) <Florent Kermarrec> * 70516c4 - Merge branch 'master' of https://github.com/enjoy-digital/litedram <> |\ | * 5820970 - frontend/crossbar: fix timvideos#49 <Florent Kermarrec> * | 71f78d9 - Fix reordering controller rejecting all commands <> * | 8f14211 - Account for CWL in write to read timing <> |/ * 5fb8afe - frontend/axi: omit bank in rdata connect <Florent Kermarrec> * 06ca53d - Merge pull request timvideos#48 from enjoy-digital/staging <enjoy-digital> |\ | * 5a4d063 - Merge branch 'master' into staging <enjoy-digital> | |\ | |/ |/| * | 5984eaa - core: change api for out-of-order. (with_reordering passed to controller and not ports). <Florent Kermarrec> * | 6e10dae - core/bankmachine/write to precharge: indicate that AL=0 <Florent Kermarrec> * | 869c8ee - Merge pull request timvideos#46 from enjoy-digital/WritePrechargeFix <enjoy-digital> |\ \ | * | 0405f41 - Update the write-to-precharge timings so it works with 1:2 <> * | | 30c32f5 - example/litedram_gen: simplify clocking with new S7PLL module, a lot easier :) <Florent Kermarrec> |/ / * | 2a3cacb - core/bankmachine: minor cleanup on trc/tras <Florent Kermarrec> * | 42ccf05 - Merge pull request timvideos#45 from enjoy-digital/tRAS_FIX <enjoy-digital> |\ \ | * | 79b1421 - Auto precharge is too pessimistic, it will wait on its own for a valid time to execute <John Sully> | * | 177d739 - Implement tRAS <John Sully> * | | 5902027 - Merge pull request timvideos#44 from enjoy-digital/tRC_Fix <enjoy-digital> |\ \ \ | |/ / | * | 5f6b857 - This adds support for tRC timing parameters <John Sully> |/ / * | 1777720 - Merge pull request timvideos#42 from enjoy-digital/HalfRateSequentialFix <enjoy-digital> |\ \ | * | 06c8c2a - The actual fix <John Sully> | * | e22580f - remove unnecessary file <John Sully> | * | c028786 - Fix overflow bug from code review <John Sully> | * | 8447d69 - We wait an extra cycle for no reason <John Sully> |/ / | * 04aa04d - Merge pull request timvideos#43 from enjoy-digital/EfficencyFixes <enjoy-digital> | |\ |/ / | * c4bd842 - Fix many bugs <John Sully> | * fa0f3b2 - Use the ready signal for cas_allowed so that arbitrators know not to iterate <John Sully> |/ * c12404e - README: Add ECC <Florent Kermarrec> * 3f4c14b - frontend/ecc: expose incident bits, change clear register name <Florent Kermarrec> * b9aadf1 - frontend/axi: remove write buffer reservation (not needed) <Florent Kermarrec> * liteeth changed from 3d86844 to 40b99ec * 40b99ec - test: use new RemoteClient import <Florent Kermarrec> * c370e9f - phy/model: remove creation/deletion of ethernet tap (now handled by the simulator) <Florent Kermarrec> * litepcie changed from 3e8de2d to a09d225 * a09d225 - test: use new RemoteClient import <Florent Kermarrec> * litesata changed from fb72044 to b78a731 * b78a731 - test: use new RemoteClient import <Florent Kermarrec> * litescope changed from 686db4f to 1634fa3 * 1634fa3 - test: use new RemoteClient import <Florent Kermarrec> * cb27987 - examples/make: look for platform in migen if not present in litex <Florent Kermarrec> * litex changed from v0.1-451-g537b0e90 to v0.1-494-g6e327cda * 6e327cda - bios/sdram: rewrite write_leveling (simplify and improve robustness) <Florent Kermarrec> * 975be668 - platforms/genesys2: add eth clock timing constraint <Florent Kermarrec> * 934a5da5 - soc/cores/clock: add expose_drp on S7PLL/S7MMCM <Florent Kermarrec> * 9097573e - Merge pull request timvideos#109 from cr1901/xip-improve <enjoy-digital> |\ | * 0ff6d586 - Distinguish crt0 variants more clearly, update BIOS to use CTR variant (as it has no .data section). <William D. Jones> | * 81060081 - integration/builder: Create EXECUTE_IN_PLACE Makefile variable to complement COPY_TO_MAIN_RAM. <William D. Jones> | * db906190 - integration/builder: Add LiteX define to generated variables (to distinguish MiSoC and LiteX). <William D. Jones> * | 082b0301 - targets: use new clock abstraction on all 7-series targets <Florent Kermarrec> * | 74e74dc0 - soc/cores/clock: different clkin_freq_range for pll and mmcm <Florent Kermarrec> * | 91d8cc2d - soc/cores/clock: different vco_freq_range for pll and mmcm <Florent Kermarrec> * | 6cd95494 - soc/core/clock: allow selecting buffer type (None, BUFG, BUFR). (default = BUFG) <Florent Kermarrec> * | 912ca323 - soc/cores/clock: create specific S7IDELAYCTRL module <Florent Kermarrec> * | baec87f5 - soc/cores/clock: add S7MMCM support <Florent Kermarrec> * | ef405249 - soc/cores/clocks/S7PLL: add speedgrade support, default to -1 (slowest) <Florent Kermarrec> * | 5415b521 - targets/arty: use new clock abstraction module (compile, untested on board) <Florent Kermarrec> * | 63fc3950 - soc/cores: init clock abstraction module <Florent Kermarrec> |/ * 70a32ed8 - sim/verilator: add multithread support (default=1) <Florent Kermarrec> * 7f0d116d - soc_core: use cpu instead of cpu_or_bridge internally (keep retro-compat for now) <Florent Kermarrec> * 22febe95 - boards/targets: uniformize things between targets <Florent Kermarrec> * 01b025aa - soc_core/get_mem_data: add endianness support and use it in builder/initialize_rom to avoid duplication <Florent Kermarrec> * b528a005 - cores/cpu: add software informations to cpu and simplify cpu_interface <Florent Kermarrec> * 2d785cb0 - boards/plarforms: fix issues found while testing simple design on all platforms <Florent Kermarrec> * 0b0e3ac1 - test/test_targets: test simple design with all platforms <Florent Kermarrec> * c88029d3 - soc_core: add uart-stub argument <Florent Kermarrec> * 0d2d3959 - setup.py: add litex_simple exec (to ease building simple design) <Florent Kermarrec> * e04530e0 - test/test_targets: update and reorganize targets <Florent Kermarrec> * e9ed7370 - ease RemoteClient import <Florent Kermarrec> * 346dcf94 - Merge pull request timvideos#108 from xobs/use-csr-accessors <enjoy-digital> |\ | * 6f25a0d8 - csr: use external csr_readl()/csr_writel() if present <Sean Cross> | * 9a252e36 - csr: use readl()/writel() accessors for accessing mmio <Sean Cross> * | 1c1d87f8 - Merge pull request timvideos#106 from cr1901/data-crt0 <Tim Ansell> |\ \ | |/ | * 9d4da737 - libbase/crt0-lm32.S: Add provisions for loading .data from flash. <William D. Jones> |/ * 01ae7d42 - README: add migen/litex clarification <Florent Kermarrec> * 15e584d8 - targets/sim: generate analyzer.csv <Florent Kermarrec> * cde72603 - targets/sim: generate csr.csv <Florent Kermarrec> * f62df502 - targets/sim: add rom-init <Florent Kermarrec> * 1dbf591e - targets/sim: add ram-init param to allow initializing ram from file (faster than tftp) <Florent Kermarrec> * 9893c246 - integration/soc_core: add get_mem_data function to read memory content from file <Florent Kermarrec> * a3eb2e40 - soc/intergration/builder: fix when no sdram <Florent Kermarrec> * 934b08ed - targets/sim: merge in a single class and ease configuration <Florent Kermarrec> * bd42b188 - Merge branch 'master' of http://github.com/enjoy-digital/litex <Florent Kermarrec> * 3e77ae78 - targets: replace MiniSoC with EthernetSoC <Florent Kermarrec> * badd9924 - targets/sim: add EtherboneSoC target (allow accessing wishbone over in simulation with litex_server) <Florent Kermarrec> * migen changed from 0.6.dev-168-gca0df1c to 0.6.dev-172-g56f359d * 56f359d - Added icebreaker platform. (timvideos#135) <Piotr Esden-Tempski> * 88e72a5 - Sayma RTM: expose clock mezzanine gpio as a connector (timvideos#134) <hartytp> * 1d3433e - Revert "Emit `default_nettype none." <Sebastien Bourdeauducq> * 4621abc - sayma rtm: add clock mezzanine GPIO (timvideos#133) <hartytp> Full submodule status -- 5eeb151a748788666534d6ea3da07f90400d24c2 edid-decode (remotes/origin/HEAD) a628956da7dc794e6e3c95b31ff9ce3af58bc763 flash_proxies (remotes/origin/HEAD) 41a8a246b65460fd1abe86d39a4107c349ad60e4 litedram (remotes/origin/HEAD) 40b99ecc05ee490d77477cba542db6d63333c390 liteeth (remotes/origin/HEAD) a09d225aafbf98b36913e10366f64ccfad3304af litepcie (remotes/origin/HEAD) b78a73110c0c26cf21bf1410329bf1e78286e929 litesata (remotes/origin/HEAD) 1634fa35bb9f2717ab355ca2e494e1d02fd489ec litescope (remotes/origin/HEAD) 0a9110f901182a1233cc4e64b6e39175f6784621 liteusb (remotes/origin/HEAD) 13d85a1fe360678bebd57c55f1b35988c655ae95 litevideo (remotes/origin/HEAD) 6e327cda2697d37b23f607a5a7712363dc60857a litex (v0.1-494-g6e327cda) 56f359d6dc5fff01b36796c8667dd4b58c0428c9 migen (0.6.dev-172-g56f359d)

* litedram changed from ea1ac4d to 208f556 * 208f556 - Merge branch 'master' of https://github.com/enjoy-digital/litedram <> |\ | * 41a8a24 - modules: express tFAW in ns <Florent Kermarrec> | * 7062068 - modules: split DDR3 in 2 categories: Chips and SO-DIMMs <Florent Kermarrec> | * 0f46dc4 - modules: add DDR3-800 timings for MT41J128M16 and use it on arty example <Florent Kermarrec> | * 426ae23 - examples/litedram_gen: add sdram_module_speedgrade parameter <Florent Kermarrec> | * 1bc016c - test: add test_examples <Florent Kermarrec> | * f7f8169 - test: update downconverter/upconverter <Florent Kermarrec> | * 8de1d91 - core: add with_bank paramteter to NativePort (cause issues on adaptation is bank is always exposed) <Florent Kermarrec> * | 69eaf84 - Fix DDR2 and below compilation failure <> |/ * 70516c4 - Merge branch 'master' of https://github.com/enjoy-digital/litedram <> |\ | * 5820970 - frontend/crossbar: fix timvideos#49 <Florent Kermarrec> * | 71f78d9 - Fix reordering controller rejecting all commands <> * | 8f14211 - Account for CWL in write to read timing <> |/ * 5fb8afe - frontend/axi: omit bank in rdata connect <Florent Kermarrec> * 06ca53d - Merge pull request timvideos#48 from enjoy-digital/staging <enjoy-digital> |\ | * 5a4d063 - Merge branch 'master' into staging <enjoy-digital> | |\ | |/ |/| * | 5984eaa - core: change api for out-of-order. (with_reordering passed to controller and not ports). <Florent Kermarrec> * | 6e10dae - core/bankmachine/write to precharge: indicate that AL=0 <Florent Kermarrec> * | 869c8ee - Merge pull request timvideos#46 from enjoy-digital/WritePrechargeFix <enjoy-digital> |\ \ | * | 0405f41 - Update the write-to-precharge timings so it works with 1:2 <> * | | 30c32f5 - example/litedram_gen: simplify clocking with new S7PLL module, a lot easier :) <Florent Kermarrec> |/ / * | 2a3cacb - core/bankmachine: minor cleanup on trc/tras <Florent Kermarrec> * | 42ccf05 - Merge pull request timvideos#45 from enjoy-digital/tRAS_FIX <enjoy-digital> |\ \ | * | 79b1421 - Auto precharge is too pessimistic, it will wait on its own for a valid time to execute <John Sully> | * | 177d739 - Implement tRAS <John Sully> * | | 5902027 - Merge pull request timvideos#44 from enjoy-digital/tRC_Fix <enjoy-digital> |\ \ \ | |/ / | * | 5f6b857 - This adds support for tRC timing parameters <John Sully> |/ / * | 1777720 - Merge pull request timvideos#42 from enjoy-digital/HalfRateSequentialFix <enjoy-digital> |\ \ | * | 06c8c2a - The actual fix <John Sully> | * | e22580f - remove unnecessary file <John Sully> | * | c028786 - Fix overflow bug from code review <John Sully> | * | 8447d69 - We wait an extra cycle for no reason <John Sully> |/ / | * 04aa04d - Merge pull request timvideos#43 from enjoy-digital/EfficencyFixes <enjoy-digital> | |\ |/ / | * c4bd842 - Fix many bugs <John Sully> | * fa0f3b2 - Use the ready signal for cas_allowed so that arbitrators know not to iterate <John Sully> |/ * c12404e - README: Add ECC <Florent Kermarrec> * 3f4c14b - frontend/ecc: expose incident bits, change clear register name <Florent Kermarrec> * b9aadf1 - frontend/axi: remove write buffer reservation (not needed) <Florent Kermarrec> * liteeth changed from 3d86844 to 40b99ec * 40b99ec - test: use new RemoteClient import <Florent Kermarrec> * c370e9f - phy/model: remove creation/deletion of ethernet tap (now handled by the simulator) <Florent Kermarrec> * litepcie changed from 3e8de2d to a09d225 * a09d225 - test: use new RemoteClient import <Florent Kermarrec> * litesata changed from fb72044 to b78a731 * b78a731 - test: use new RemoteClient import <Florent Kermarrec> * litescope changed from 686db4f to 1634fa3 * 1634fa3 - test: use new RemoteClient import <Florent Kermarrec> * cb27987 - examples/make: look for platform in migen if not present in litex <Florent Kermarrec> * migen changed from 0.6.dev-168-gca0df1c to 0.6.dev-172-g56f359d * 56f359d - Added icebreaker platform. (timvideos#135) <Piotr Esden-Tempski> * 88e72a5 - Sayma RTM: expose clock mezzanine gpio as a connector (timvideos#134) <hartytp> * 1d3433e - Revert "Emit `default_nettype none." <Sebastien Bourdeauducq> * 4621abc - sayma rtm: add clock mezzanine GPIO (timvideos#133) <hartytp> Full submodule status -- 5eeb151a748788666534d6ea3da07f90400d24c2 edid-decode (remotes/origin/HEAD) a628956da7dc794e6e3c95b31ff9ce3af58bc763 flash_proxies (remotes/origin/HEAD) 208f5562d1e3825ddac6e73d14394d3310f2d239 litedram (remotes/origin/HEAD) 40b99ecc05ee490d77477cba542db6d63333c390 liteeth (remotes/origin/HEAD) a09d225aafbf98b36913e10366f64ccfad3304af litepcie (remotes/origin/HEAD) b78a73110c0c26cf21bf1410329bf1e78286e929 litesata (remotes/origin/HEAD) 1634fa35bb9f2717ab355ca2e494e1d02fd489ec litescope (remotes/origin/HEAD) 0a9110f901182a1233cc4e64b6e39175f6784621 liteusb (remotes/origin/HEAD) 13d85a1fe360678bebd57c55f1b35988c655ae95 litevideo (remotes/origin/HEAD) 6e327cda2697d37b23f607a5a7712363dc60857a litex (v0.1-494-g6e327cda) 56f359d6dc5fff01b36796c8667dd4b58c0428c9 migen (0.6.dev-172-g56f359d)

* litedram changed from ea1ac4d to eddce76 * eddce76 - Adding tCCD for DDR2 modules. <Tim 'mithro' Ansell> * 208f556 - Merge branch 'master' of https://github.com/enjoy-digital/litedram <> |\ | * 41a8a24 - modules: express tFAW in ns <Florent Kermarrec> | * 7062068 - modules: split DDR3 in 2 categories: Chips and SO-DIMMs <Florent Kermarrec> | * 0f46dc4 - modules: add DDR3-800 timings for MT41J128M16 and use it on arty example <Florent Kermarrec> | * 426ae23 - examples/litedram_gen: add sdram_module_speedgrade parameter <Florent Kermarrec> | * 1bc016c - test: add test_examples <Florent Kermarrec> | * f7f8169 - test: update downconverter/upconverter <Florent Kermarrec> | * 8de1d91 - core: add with_bank paramteter to NativePort (cause issues on adaptation is bank is always exposed) <Florent Kermarrec> * | 69eaf84 - Fix DDR2 and below compilation failure <> |/ * 70516c4 - Merge branch 'master' of https://github.com/enjoy-digital/litedram <> |\ | * 5820970 - frontend/crossbar: fix timvideos#49 <Florent Kermarrec> * | 71f78d9 - Fix reordering controller rejecting all commands <> * | 8f14211 - Account for CWL in write to read timing <> |/ * 5fb8afe - frontend/axi: omit bank in rdata connect <Florent Kermarrec> * 06ca53d - Merge pull request timvideos#48 from enjoy-digital/staging <enjoy-digital> |\ | * 5a4d063 - Merge branch 'master' into staging <enjoy-digital> | |\ | |/ |/| * | 5984eaa - core: change api for out-of-order. (with_reordering passed to controller and not ports). <Florent Kermarrec> * | 6e10dae - core/bankmachine/write to precharge: indicate that AL=0 <Florent Kermarrec> * | 869c8ee - Merge pull request timvideos#46 from enjoy-digital/WritePrechargeFix <enjoy-digital> |\ \ | * | 0405f41 - Update the write-to-precharge timings so it works with 1:2 <> * | | 30c32f5 - example/litedram_gen: simplify clocking with new S7PLL module, a lot easier :) <Florent Kermarrec> |/ / * | 2a3cacb - core/bankmachine: minor cleanup on trc/tras <Florent Kermarrec> * | 42ccf05 - Merge pull request timvideos#45 from enjoy-digital/tRAS_FIX <enjoy-digital> |\ \ | * | 79b1421 - Auto precharge is too pessimistic, it will wait on its own for a valid time to execute <John Sully> | * | 177d739 - Implement tRAS <John Sully> * | | 5902027 - Merge pull request timvideos#44 from enjoy-digital/tRC_Fix <enjoy-digital> |\ \ \ | |/ / | * | 5f6b857 - This adds support for tRC timing parameters <John Sully> |/ / * | 1777720 - Merge pull request timvideos#42 from enjoy-digital/HalfRateSequentialFix <enjoy-digital> |\ \ | * | 06c8c2a - The actual fix <John Sully> | * | e22580f - remove unnecessary file <John Sully> | * | c028786 - Fix overflow bug from code review <John Sully> | * | 8447d69 - We wait an extra cycle for no reason <John Sully> |/ / | * 04aa04d - Merge pull request timvideos#43 from enjoy-digital/EfficencyFixes <enjoy-digital> | |\ |/ / | * c4bd842 - Fix many bugs <John Sully> | * fa0f3b2 - Use the ready signal for cas_allowed so that arbitrators know not to iterate <John Sully> |/ * c12404e - README: Add ECC <Florent Kermarrec> * 3f4c14b - frontend/ecc: expose incident bits, change clear register name <Florent Kermarrec> * b9aadf1 - frontend/axi: remove write buffer reservation (not needed) <Florent Kermarrec> * liteeth changed from 3d86844 to 40b99ec * 40b99ec - test: use new RemoteClient import <Florent Kermarrec> * c370e9f - phy/model: remove creation/deletion of ethernet tap (now handled by the simulator) <Florent Kermarrec> * litepcie changed from 3e8de2d to a09d225 * a09d225 - test: use new RemoteClient import <Florent Kermarrec> * litesata changed from fb72044 to b78a731 * b78a731 - test: use new RemoteClient import <Florent Kermarrec> * litescope changed from 686db4f to 1634fa3 * 1634fa3 - test: use new RemoteClient import <Florent Kermarrec> * cb27987 - examples/make: look for platform in migen if not present in litex <Florent Kermarrec> * migen changed from 0.6.dev-168-gca0df1c to 0.6.dev-173-gd3b875b * d3b875b - Fixed on board green led pin number. Added "multi" led. <Piotr Esden-Tempski> * 56f359d - Added icebreaker platform. (timvideos#135) <Piotr Esden-Tempski> * 88e72a5 - Sayma RTM: expose clock mezzanine gpio as a connector (timvideos#134) <hartytp> * 1d3433e - Revert "Emit `default_nettype none." <Sebastien Bourdeauducq> * 4621abc - sayma rtm: add clock mezzanine GPIO (timvideos#133) <hartytp> Full submodule status -- 5eeb151a748788666534d6ea3da07f90400d24c2 edid-decode (remotes/origin/HEAD) a628956da7dc794e6e3c95b31ff9ce3af58bc763 flash_proxies (remotes/origin/HEAD) eddce76ee4a5bdb84e09020983aaa273b9cd5342 litedram (heads/master) 40b99ecc05ee490d77477cba542db6d63333c390 liteeth (remotes/origin/HEAD) a09d225aafbf98b36913e10366f64ccfad3304af litepcie (remotes/origin/HEAD) b78a73110c0c26cf21bf1410329bf1e78286e929 litesata (remotes/origin/HEAD) 1634fa35bb9f2717ab355ca2e494e1d02fd489ec litescope (remotes/origin/HEAD) 0a9110f901182a1233cc4e64b6e39175f6784621 liteusb (remotes/origin/HEAD) 13d85a1fe360678bebd57c55f1b35988c655ae95 litevideo (remotes/origin/HEAD) 6e327cda2697d37b23f607a5a7712363dc60857a litex (v0.1-494-g6e327cda) d3b875b46eee4d34e093e63cd769bdfaae0da3df migen (0.6.dev-173-gd3b875b)

* litedram changed from ea1ac4d to 6c7a804 * 6c7a804 - Adding tCCD for DDR2 modules. <Tim 'mithro' Ansell> * 208f556 - Merge branch 'master' of https://github.com/enjoy-digital/litedram <> |\ | * 41a8a24 - modules: express tFAW in ns <Florent Kermarrec> | * 7062068 - modules: split DDR3 in 2 categories: Chips and SO-DIMMs <Florent Kermarrec> | * 0f46dc4 - modules: add DDR3-800 timings for MT41J128M16 and use it on arty example <Florent Kermarrec> | * 426ae23 - examples/litedram_gen: add sdram_module_speedgrade parameter <Florent Kermarrec> | * 1bc016c - test: add test_examples <Florent Kermarrec> | * f7f8169 - test: update downconverter/upconverter <Florent Kermarrec> | * 8de1d91 - core: add with_bank paramteter to NativePort (cause issues on adaptation is bank is always exposed) <Florent Kermarrec> * | 69eaf84 - Fix DDR2 and below compilation failure <> |/ * 70516c4 - Merge branch 'master' of https://github.com/enjoy-digital/litedram <> |\ | * 5820970 - frontend/crossbar: fix timvideos#49 <Florent Kermarrec> * | 71f78d9 - Fix reordering controller rejecting all commands <> * | 8f14211 - Account for CWL in write to read timing <> |/ * 5fb8afe - frontend/axi: omit bank in rdata connect <Florent Kermarrec> * 06ca53d - Merge pull request timvideos#48 from enjoy-digital/staging <enjoy-digital> |\ | * 5a4d063 - Merge branch 'master' into staging <enjoy-digital> | |\ | |/ |/| * | 5984eaa - core: change api for out-of-order. (with_reordering passed to controller and not ports). <Florent Kermarrec> * | 6e10dae - core/bankmachine/write to precharge: indicate that AL=0 <Florent Kermarrec> * | 869c8ee - Merge pull request timvideos#46 from enjoy-digital/WritePrechargeFix <enjoy-digital> |\ \ | * | 0405f41 - Update the write-to-precharge timings so it works with 1:2 <> * | | 30c32f5 - example/litedram_gen: simplify clocking with new S7PLL module, a lot easier :) <Florent Kermarrec> |/ / * | 2a3cacb - core/bankmachine: minor cleanup on trc/tras <Florent Kermarrec> * | 42ccf05 - Merge pull request timvideos#45 from enjoy-digital/tRAS_FIX <enjoy-digital> |\ \ | * | 79b1421 - Auto precharge is too pessimistic, it will wait on its own for a valid time to execute <John Sully> | * | 177d739 - Implement tRAS <John Sully> * | | 5902027 - Merge pull request timvideos#44 from enjoy-digital/tRC_Fix <enjoy-digital> |\ \ \ | |/ / | * | 5f6b857 - This adds support for tRC timing parameters <John Sully> |/ / * | 1777720 - Merge pull request timvideos#42 from enjoy-digital/HalfRateSequentialFix <enjoy-digital> |\ \ | * | 06c8c2a - The actual fix <John Sully> | * | e22580f - remove unnecessary file <John Sully> | * | c028786 - Fix overflow bug from code review <John Sully> | * | 8447d69 - We wait an extra cycle for no reason <John Sully> |/ / | * 04aa04d - Merge pull request timvideos#43 from enjoy-digital/EfficencyFixes <enjoy-digital> | |\ |/ / | * c4bd842 - Fix many bugs <John Sully> | * fa0f3b2 - Use the ready signal for cas_allowed so that arbitrators know not to iterate <John Sully> |/ * c12404e - README: Add ECC <Florent Kermarrec> * 3f4c14b - frontend/ecc: expose incident bits, change clear register name <Florent Kermarrec> * b9aadf1 - frontend/axi: remove write buffer reservation (not needed) <Florent Kermarrec> * liteeth changed from 3d86844 to 40b99ec * 40b99ec - test: use new RemoteClient import <Florent Kermarrec> * c370e9f - phy/model: remove creation/deletion of ethernet tap (now handled by the simulator) <Florent Kermarrec> * litepcie changed from 3e8de2d to a09d225 * a09d225 - test: use new RemoteClient import <Florent Kermarrec> * litesata changed from fb72044 to b78a731 * b78a731 - test: use new RemoteClient import <Florent Kermarrec> * litescope changed from 686db4f to 1634fa3 * 1634fa3 - test: use new RemoteClient import <Florent Kermarrec> * cb27987 - examples/make: look for platform in migen if not present in litex <Florent Kermarrec> * migen changed from 0.6.dev-168-gca0df1c to 0.6.dev-173-gd3b875b * d3b875b - Fixed on board green led pin number. Added "multi" led. <Piotr Esden-Tempski> * 56f359d - Added icebreaker platform. (timvideos#135) <Piotr Esden-Tempski> * 88e72a5 - Sayma RTM: expose clock mezzanine gpio as a connector (timvideos#134) <hartytp> * 1d3433e - Revert "Emit `default_nettype none." <Sebastien Bourdeauducq> * 4621abc - sayma rtm: add clock mezzanine GPIO (timvideos#133) <hartytp> Full submodule status -- 5eeb151a748788666534d6ea3da07f90400d24c2 edid-decode (remotes/origin/HEAD) a628956da7dc794e6e3c95b31ff9ce3af58bc763 flash_proxies (remotes/origin/HEAD) 6c7a804986d8916bdc3d97ba2181c00787a5a91b litedram (heads/master) 40b99ecc05ee490d77477cba542db6d63333c390 liteeth (remotes/origin/HEAD) a09d225aafbf98b36913e10366f64ccfad3304af litepcie (remotes/origin/HEAD) b78a73110c0c26cf21bf1410329bf1e78286e929 litesata (remotes/origin/HEAD) 1634fa35bb9f2717ab355ca2e494e1d02fd489ec litescope (remotes/origin/HEAD) 0a9110f901182a1233cc4e64b6e39175f6784621 liteusb (remotes/origin/HEAD) 13d85a1fe360678bebd57c55f1b35988c655ae95 litevideo (remotes/origin/HEAD) 6e327cda2697d37b23f607a5a7712363dc60857a litex (v0.1-494-g6e327cda) d3b875b46eee4d34e093e63cd769bdfaae0da3df migen (0.6.dev-173-gd3b875b)

* litedram changed from ea1ac4d to 5b02791 * 5b02791 - modules: add tCCD to all modules <Florent Kermarrec> * 6c7a804 - Adding tCCD for DDR2 modules. <Tim 'mithro' Ansell> * 208f556 - Merge branch 'master' of https://github.com/enjoy-digital/litedram <> |\ | * 41a8a24 - modules: express tFAW in ns <Florent Kermarrec> | * 7062068 - modules: split DDR3 in 2 categories: Chips and SO-DIMMs <Florent Kermarrec> | * 0f46dc4 - modules: add DDR3-800 timings for MT41J128M16 and use it on arty example <Florent Kermarrec> | * 426ae23 - examples/litedram_gen: add sdram_module_speedgrade parameter <Florent Kermarrec> | * 1bc016c - test: add test_examples <Florent Kermarrec> | * f7f8169 - test: update downconverter/upconverter <Florent Kermarrec> | * 8de1d91 - core: add with_bank paramteter to NativePort (cause issues on adaptation is bank is always exposed) <Florent Kermarrec> * | 69eaf84 - Fix DDR2 and below compilation failure <> |/ * 70516c4 - Merge branch 'master' of https://github.com/enjoy-digital/litedram <> |\ | * 5820970 - frontend/crossbar: fix timvideos#49 <Florent Kermarrec> * | 71f78d9 - Fix reordering controller rejecting all commands <> * | 8f14211 - Account for CWL in write to read timing <> |/ * 5fb8afe - frontend/axi: omit bank in rdata connect <Florent Kermarrec> * 06ca53d - Merge pull request timvideos#48 from enjoy-digital/staging <enjoy-digital> |\ | * 5a4d063 - Merge branch 'master' into staging <enjoy-digital> | |\ | |/ |/| * | 5984eaa - core: change api for out-of-order. (with_reordering passed to controller and not ports). <Florent Kermarrec> * | 6e10dae - core/bankmachine/write to precharge: indicate that AL=0 <Florent Kermarrec> * | 869c8ee - Merge pull request timvideos#46 from enjoy-digital/WritePrechargeFix <enjoy-digital> |\ \ | * | 0405f41 - Update the write-to-precharge timings so it works with 1:2 <> * | | 30c32f5 - example/litedram_gen: simplify clocking with new S7PLL module, a lot easier :) <Florent Kermarrec> |/ / * | 2a3cacb - core/bankmachine: minor cleanup on trc/tras <Florent Kermarrec> * | 42ccf05 - Merge pull request timvideos#45 from enjoy-digital/tRAS_FIX <enjoy-digital> |\ \ | * | 79b1421 - Auto precharge is too pessimistic, it will wait on its own for a valid time to execute <John Sully> | * | 177d739 - Implement tRAS <John Sully> * | | 5902027 - Merge pull request timvideos#44 from enjoy-digital/tRC_Fix <enjoy-digital> |\ \ \ | |/ / | * | 5f6b857 - This adds support for tRC timing parameters <John Sully> |/ / * | 1777720 - Merge pull request timvideos#42 from enjoy-digital/HalfRateSequentialFix <enjoy-digital> |\ \ | * | 06c8c2a - The actual fix <John Sully> | * | e22580f - remove unnecessary file <John Sully> | * | c028786 - Fix overflow bug from code review <John Sully> | * | 8447d69 - We wait an extra cycle for no reason <John Sully> |/ / | * 04aa04d - Merge pull request timvideos#43 from enjoy-digital/EfficencyFixes <enjoy-digital> | |\ |/ / | * c4bd842 - Fix many bugs <John Sully> | * fa0f3b2 - Use the ready signal for cas_allowed so that arbitrators know not to iterate <John Sully> |/ * c12404e - README: Add ECC <Florent Kermarrec> * 3f4c14b - frontend/ecc: expose incident bits, change clear register name <Florent Kermarrec> * b9aadf1 - frontend/axi: remove write buffer reservation (not needed) <Florent Kermarrec> * liteeth changed from 3d86844 to 40b99ec * 40b99ec - test: use new RemoteClient import <Florent Kermarrec> * c370e9f - phy/model: remove creation/deletion of ethernet tap (now handled by the simulator) <Florent Kermarrec> * litepcie changed from 3e8de2d to a09d225 * a09d225 - test: use new RemoteClient import <Florent Kermarrec> * litesata changed from fb72044 to b78a731 * b78a731 - test: use new RemoteClient import <Florent Kermarrec> * litescope changed from 686db4f to 1634fa3 * 1634fa3 - test: use new RemoteClient import <Florent Kermarrec> * cb27987 - examples/make: look for platform in migen if not present in litex <Florent Kermarrec> * migen changed from 0.6.dev-168-gca0df1c to 0.6.dev-173-gd3b875b * d3b875b - Fixed on board green led pin number. Added "multi" led. <Piotr Esden-Tempski> * 56f359d - Added icebreaker platform. (timvideos#135) <Piotr Esden-Tempski> * 88e72a5 - Sayma RTM: expose clock mezzanine gpio as a connector (timvideos#134) <hartytp> * 1d3433e - Revert "Emit `default_nettype none." <Sebastien Bourdeauducq> * 4621abc - sayma rtm: add clock mezzanine GPIO (timvideos#133) <hartytp> Full submodule status -- 5eeb151a748788666534d6ea3da07f90400d24c2 edid-decode (remotes/origin/HEAD) a628956da7dc794e6e3c95b31ff9ce3af58bc763 flash_proxies (remotes/origin/HEAD) 5b02791580db9d1bae64b6524b7aca3540d89937 litedram (remotes/origin/HEAD) 40b99ecc05ee490d77477cba542db6d63333c390 liteeth (remotes/origin/HEAD) a09d225aafbf98b36913e10366f64ccfad3304af litepcie (remotes/origin/HEAD) b78a73110c0c26cf21bf1410329bf1e78286e929 litesata (remotes/origin/HEAD) 1634fa35bb9f2717ab355ca2e494e1d02fd489ec litescope (remotes/origin/HEAD) 0a9110f901182a1233cc4e64b6e39175f6784621 liteusb (remotes/origin/HEAD) 13d85a1fe360678bebd57c55f1b35988c655ae95 litevideo (remotes/origin/HEAD) 6e327cda2697d37b23f607a5a7712363dc60857a litex (v0.1-494-g6e327cda) d3b875b46eee4d34e093e63cd769bdfaae0da3df migen (0.6.dev-173-gd3b875b)

* litedram changed from edd5e0e to c4ac887 * c4ac887 - Merge pull request timvideos#206 from antmicro/jboc/gensdrphy <enjoy-digital> * 2c5fc66 - phy/gensdrphy: fix problems with half-rate phy, tested on minispartan6 <Jędrzej Boczar> * 7f55e2e - phy/gensdrphy: add half-rate PHY <Jędrzej Boczar> * liteeth changed from dbe15f1 to 792013a * 792013a - mac/sram: avoid asynchronous read port on LiteEthMACSRAMReader (fix the resource usage issue identified in timvideos#43). <Florent Kermarrec> * 1d76d02 - frontend: rename tty to stream (tty was too specific since modules can be used for any kind of data stream). <Florent Kermarrec> * litepcie changed from 5668679 to 0b6a4bb * 0b6a4bb - software/kernel/main: enable up to 8 dma channels. <Florent Kermarrec> * f106f74 - software/user/litepcie_util: reset dma_test errors to 0 on each loop. <Florent Kermarrec> * 4d506fb - litepcie_gen: remove CSR software reset (no longer handled by software. <Florent Kermarrec> * f258b88 - phy/ultrascale: fix padding on s_axis_cc_header0 (requesterid was shifted by 1-bit). <Florent Kermarrec> * ccdd7a2 - core/msi/LitePCIeMSIX: avoid reserved registers when width > 32. <Florent Kermarrec> * litex changed from e7646416 to ac35e158 * ac35e158 - bios/boot: add bootargs support on netboot/sdcardboot to optionally specify r1/r2/r3/addr. <Florent Kermarrec> * ee4b1d81 - Merge pull request timvideos#594 from antmicro/jboc/axi-lite <enjoy-digital> |\ | * 229da572 - soc/interconnect/axi: propagate response errors in AXILiteDownConverter <Jędrzej Boczar> | * 93bcc94b - soc/interconnect/axi: implement AXILite down-converter <Jędrzej Boczar> * | 21c48eed - Merge pull request timvideos#593 from antmicro/jboc/axi-lite <enjoy-digital> |\| | * 0be607da - soc/integration: revert `bus` argument for add_ram/add_rom <Jędrzej Boczar> | * 2700ec3c - soc/integration: use AXILiteConverter (dummy implementation) in add_adapter() <Jędrzej Boczar> | * f3072d49 - soc/interconnect/axi: add connect methods for convenience <Jędrzej Boczar> | * 78a631f3 - test/axi: add AXILite2CSR and AXILiteSRAM tests <Jędrzej Boczar> | * a5be2cd2 - soc/interconnect/axi: improve SRAM/CSR access speed <Jędrzej Boczar> | * d8a242d8 - soc/interconnect: add AXILite SRAM <Jędrzej Boczar> | * b692b2a3 - soc/interconnect: add AXILite2CSR bridge <Jędrzej Boczar> | * 35149c4e - soc/integration: update add_adapter to convert between AXILite/Wishbone <Jędrzej Boczar> * | e12bebb8 - Merge pull request timvideos#592 from antmicro/fix-symbiflow-makefile <enjoy-digital> |\ \ | |/ |/| | * 3f7568de - symbiflow: changed toolchain command names in Makefile <Alessandro Comodi> |/ * 6671eb62 - build/lattice/trellis: set default spimode to None (--spimode not passed to ecppack) as default instead of fast-read. <Florent Kermarrec> * ae3c78f6 - build/lattice/trellis: fix spimode typo. <Florent Kermarrec> * 7c381dad - Merge pull request timvideos#588 from oskirby/trellis-spimode <enjoy-digital> * 0aec5b0f - trellis: Add option to select SPI mode. <Owen Kirby> * litex-boards changed from 1f98bc5 to 165f9ea * 165f9ea - Merge pull request timvideos#91 from antmicro/jboc/gensdrphy <enjoy-digital> |\ | * 02f53e6 - targets/minispartan6: add support for HalfRateGENSDRPHY <Jędrzej Boczar> * 82f4553 - Merge pull request timvideos#90 from jersey99/master <enjoy-digital> * 44ad902 - platforms/kc705.py: LPC DP0_M2C/C2M diff pair <Vamsi K Vytla> * migen changed from 0.6.dev-351-gfa7bed2 to 0.6.dev-352-g12e7ba6 * 12e7ba6 - Fix Si5324 reset. <Paweł Kulik> Full submodule status -- 2942d0652a89646c5225bee15dd55cc3b0871766 VexRiscv (1.0.1-417-g2942d06) 3a6108a75be356a3dc53760d22782f1323248b6b edid-decode (heads/master) 3a06aa84b62ad24467fb0d2c6ceddf565e9ea447 flash_proxies (heads/master) c4ac887ec20f585f194e74878445334c024244de litedram (2020.04-68-gc4ac887) 792013a1756ea50608726ee86989ec38cfc35a8b liteeth (2020.04-21-g792013a) 6fdd02058fba29008c90b162e0ef707dce15ebeb liteiclink (2020.04) 0b6a4bb6e742fd4de38d7ca3674f91acc5985b35 litepcie (2020.04-56-g0b6a4bb) b36d3a33fbbfcffdb77a7a9e05bc8121387858d3 litesata (2020.04-1-gb36d3a3) 15179cb46f68bff1679631a8bade6f7e1607a40a litescope (2020.04-2-g15179cb) 7457a29b1a47fe15e81fa37f3bbdd510788f1d53 liteusb (heads/master) 41f30143075ece3fff5c33a332ed067d1837cbb3 litevideo (2020.04) ac35e158c1a908f8ea35ded97587c78a72babcae litex (2020.04-480-gac35e158) 165f9eacde3bf1cd97a77f3ed692003150831ceb litex-boards (2020.04-129-g165f9ea) f1792587a9b50732578e0166cb5d1d83b126cfa6 litex-renode (remotes/origin/HEAD) 12e7ba6a4c19ee65ff9e042747220972aecc05ac migen (0.6.dev-352-g12e7ba6) 8f5a253b22cd4ebcd56304a3662f4c70e3b34ed5 nmigen (v0.1-69-g8f5a253) 48333804e40c7c9c1c8d5b2e70ba75f4b646d8f0 pythondata-cpu-lm32 (2020.04-5-g4833380) 4731142284cf87e89b21fb35ceff1139f2f89227 pythondata-cpu-minerva (heads/master) af561171f5fc8c684537897f12ef0f429e38624b pythondata-cpu-mor1kx (2020.04-5-gaf56117) 88974894c800ee2e827db47865e0611a07ff40d7 pythondata-cpu-picorv32 (2020.04-5-g8897489) 654057b2f5cec0f9fc99487dff67861f76fcbe7e pythondata-cpu-vexriscv (2020.04-7-g654057b) 7cfcaed2e726027fd622650b58dd77e47c495ee0 pythondata-software-compiler_rt (2020.04-5-g7cfcaed2)

* litedram changed from edd5e0e to f51052f * f51052f - core/controller: fix burst_length regression introduced by timvideos#206. <Florent Kermarrec> * c4ac887 - Merge pull request timvideos#206 from antmicro/jboc/gensdrphy <enjoy-digital> * 2c5fc66 - phy/gensdrphy: fix problems with half-rate phy, tested on minispartan6 <Jędrzej Boczar> * 7f55e2e - phy/gensdrphy: add half-rate PHY <Jędrzej Boczar> * liteeth changed from dbe15f1 to 792013a * 792013a - mac/sram: avoid asynchronous read port on LiteEthMACSRAMReader (fix the resource usage issue identified in timvideos#43). <Florent Kermarrec> * 1d76d02 - frontend: rename tty to stream (tty was too specific since modules can be used for any kind of data stream). <Florent Kermarrec> * litepcie changed from 5668679 to 0b6a4bb * 0b6a4bb - software/kernel/main: enable up to 8 dma channels. <Florent Kermarrec> * f106f74 - software/user/litepcie_util: reset dma_test errors to 0 on each loop. <Florent Kermarrec> * 4d506fb - litepcie_gen: remove CSR software reset (no longer handled by software. <Florent Kermarrec> * f258b88 - phy/ultrascale: fix padding on s_axis_cc_header0 (requesterid was shifted by 1-bit). <Florent Kermarrec> * ccdd7a2 - core/msi/LitePCIeMSIX: avoid reserved registers when width > 32. <Florent Kermarrec> * litex changed from e7646416 to 9fc488bd * 9fc488bd - Merge pull request timvideos#597 from antmicro/jboc/litex-buildenv-add-adapter-fix <enjoy-digital> |\ | * 07bc589c - fix/Vivado: don't instantiate wishbone.Converter in add_adapter when not needed <Jędrzej Boczar> * | b9251950 - Merge pull request timvideos#595 from betrusted-io/master <enjoy-digital> |\ \ | * | 53a567da - wire up missing register bits. <bunnie> * | | 87d7f6e7 - Merge pull request timvideos#598 from sergachev/master <enjoy-digital> |\ \ \ | |_|/ |/| | | * | 8656ea9b - interconnect/csr_bus: fix paged access warning <Ilia Sergachev> |/ / * | 4a18b828 - software/liblitesdcard/spisdcard: remove optimization on receive_block (not working on all configs) and increase max clk_freq to 20MHz. <Florent Kermarrec> * | 100aa5a4 - soc/cores/spi/SPIMaster: rewrite/simplify. - Make sure MOSI is latched on start, MISO is stable during Xfer (last value). - Allow clk_divider down to 2. - improve test errors reporting with hex() on AssertEqual. <Florent Kermarrec> |/ * 63c19ff4 - liblitesdcard/spisdcard: update comments. <Florent Kermarrec> * 1f34f6ef - soc/cores/spi: make sure done and miso are synchronous. <Florent Kermarrec> * 754f140a - spisdcard: revert to 8-bit SPI, optimize spisdcardreceive_block and reduce clk to 12.5MHz for now. <Florent Kermarrec> * 8143f1a0 - soc/cores/spi: make sure miso is stable during xfer. <Florent Kermarrec> * ac35e158 - bios/boot: add bootargs support on netboot/sdcardboot to optionally specify r1/r2/r3/addr. <Florent Kermarrec> * ee4b1d81 - Merge pull request timvideos#594 from antmicro/jboc/axi-lite <enjoy-digital> |\ | * 229da572 - soc/interconnect/axi: propagate response errors in AXILiteDownConverter <Jędrzej Boczar> | * 93bcc94b - soc/interconnect/axi: implement AXILite down-converter <Jędrzej Boczar> * | 21c48eed - Merge pull request timvideos#593 from antmicro/jboc/axi-lite <enjoy-digital> |\| | * 0be607da - soc/integration: revert `bus` argument for add_ram/add_rom <Jędrzej Boczar> | * 2700ec3c - soc/integration: use AXILiteConverter (dummy implementation) in add_adapter() <Jędrzej Boczar> | * f3072d49 - soc/interconnect/axi: add connect methods for convenience <Jędrzej Boczar> | * 78a631f3 - test/axi: add AXILite2CSR and AXILiteSRAM tests <Jędrzej Boczar> | * a5be2cd2 - soc/interconnect/axi: improve SRAM/CSR access speed <Jędrzej Boczar> | * d8a242d8 - soc/interconnect: add AXILite SRAM <Jędrzej Boczar> | * b692b2a3 - soc/interconnect: add AXILite2CSR bridge <Jędrzej Boczar> | * 35149c4e - soc/integration: update add_adapter to convert between AXILite/Wishbone <Jędrzej Boczar> * | e12bebb8 - Merge pull request timvideos#592 from antmicro/fix-symbiflow-makefile <enjoy-digital> |\ \ | |/ |/| | * 3f7568de - symbiflow: changed toolchain command names in Makefile <Alessandro Comodi> |/ * 6671eb62 - build/lattice/trellis: set default spimode to None (--spimode not passed to ecppack) as default instead of fast-read. <Florent Kermarrec> * ae3c78f6 - build/lattice/trellis: fix spimode typo. <Florent Kermarrec> * 7c381dad - Merge pull request timvideos#588 from oskirby/trellis-spimode <enjoy-digital> * 0aec5b0f - trellis: Add option to select SPI mode. <Owen Kirby> * litex-boards changed from 1f98bc5 to 2ce24df * 2ce24df - platforms/genesys2: add internal_vref to 0.750v on bank 34 (DDR3). <Florent Kermarrec> * 135c387 - platforms/ulx3s: add assertion for supported devices. <Florent Kermarrec> * 851378f - platforms/trellisboard: move ddram_vtt_en. <Florent Kermarrec> * 165f9ea - Merge pull request timvideos#91 from antmicro/jboc/gensdrphy <enjoy-digital> |\ | * 02f53e6 - targets/minispartan6: add support for HalfRateGENSDRPHY <Jędrzej Boczar> * 82f4553 - Merge pull request timvideos#90 from jersey99/master <enjoy-digital> * 44ad902 - platforms/kc705.py: LPC DP0_M2C/C2M diff pair <Vamsi K Vytla> * migen changed from 0.6.dev-351-gfa7bed2 to 0.6.dev-354-g7bc4eb1 * 7bc4eb1 - xilinx: add DDRInput for Spartan6 (timvideos#214) <Thomas Spurden> * 731c192 - metlino: add SFP CTL pins <Harry Ho> * 12e7ba6 - Fix Si5324 reset. <Paweł Kulik> Full submodule status -- 2942d0652a89646c5225bee15dd55cc3b0871766 VexRiscv (1.0.1-417-g2942d06) 3a6108a75be356a3dc53760d22782f1323248b6b edid-decode (heads/master) 3a06aa84b62ad24467fb0d2c6ceddf565e9ea447 flash_proxies (heads/master) f51052f8b737156d1e257eff7cd3259cb56d0d1b litedram (2020.04-69-gf51052f) 792013a1756ea50608726ee86989ec38cfc35a8b liteeth (2020.04-21-g792013a) 6fdd02058fba29008c90b162e0ef707dce15ebeb liteiclink (2020.04) 0b6a4bb6e742fd4de38d7ca3674f91acc5985b35 litepcie (2020.04-56-g0b6a4bb) b36d3a33fbbfcffdb77a7a9e05bc8121387858d3 litesata (2020.04-1-gb36d3a3) 15179cb46f68bff1679631a8bade6f7e1607a40a litescope (2020.04-2-g15179cb) 7457a29b1a47fe15e81fa37f3bbdd510788f1d53 liteusb (heads/master) 41f30143075ece3fff5c33a332ed067d1837cbb3 litevideo (2020.04) 9fc488bdf670c69193a6fa14e5f0c218db8b0ffe litex (2020.04-492-g9fc488bd) 2ce24df76dda20cff9ac40c334300d5dc1311d60 litex-boards (2020.04-132-g2ce24df) f1792587a9b50732578e0166cb5d1d83b126cfa6 litex-renode (remotes/origin/HEAD) 7bc4eb1387b39159a74c1dbd1b820728e0bfbbaa migen (0.6.dev-354-g7bc4eb1) 8f5a253b22cd4ebcd56304a3662f4c70e3b34ed5 nmigen (v0.1-69-g8f5a253) 48333804e40c7c9c1c8d5b2e70ba75f4b646d8f0 pythondata-cpu-lm32 (2020.04-5-g4833380) 4731142284cf87e89b21fb35ceff1139f2f89227 pythondata-cpu-minerva (heads/master) af561171f5fc8c684537897f12ef0f429e38624b pythondata-cpu-mor1kx (2020.04-5-gaf56117) 88974894c800ee2e827db47865e0611a07ff40d7 pythondata-cpu-picorv32 (2020.04-5-g8897489) 654057b2f5cec0f9fc99487dff67861f76fcbe7e pythondata-cpu-vexriscv (2020.04-7-g654057b) 7cfcaed2e726027fd622650b58dd77e47c495ee0 pythondata-software-compiler_rt (2020.04-5-g7cfcaed2)

ray-bot bot added the in-progress label Sep 8, 2018

mithro mentioned this issue Sep 8, 2018

tools: Read the BIOS maxsize from the SoC. #51

Merged

label-issues-targeted-by-open-prs bot added the pull request open label Sep 8, 2018

mithro added a commit to mithro/litex-buildenv that referenced this issue Sep 8, 2018

tools: Read the BIOS maxsize from the SoC.

8c17b79

Means the larger BIOS size on or1k should be understood by `mkimage.py` command. Fixes timvideos#43.

mithro closed this as completed in #51 Sep 8, 2018

ray-bot bot added done and removed in-progress labels Sep 8, 2018

label-issues-targeted-by-open-prs bot removed the pull request open label Sep 8, 2018

mithro mentioned this issue Sep 30, 2018

Updating submodules. #75

Merged

Provide feedback

Saved searches

Use saved searches to filter your results more quickly

or1k bios is too large to fit in ROM region #43

or1k bios is too large to fit in ROM region #43

mithro commented Aug 28, 2018

mithro commented Aug 28, 2018 •

edited by unfurl-links bot

ray-bot bot commented Sep 8, 2018

or1k bios is too large to fit in ROM region #43

or1k bios is too large to fit in ROM region #43

Comments

mithro commented Aug 28, 2018

mithro commented Aug 28, 2018 • edited by unfurl-links bot

ray-bot bot commented Sep 8, 2018

mithro commented Aug 28, 2018 •

edited by unfurl-links bot