Playing around with Hardware Description Languages. Nothing too serious, just taking a look how all of this works.

How?

All simulation is done via Verilator and the results are displayable with GTKWave. Make sure that you have both of these dependencies installed (and beware openSUSE's weird default installation path for Verilator!).

Each design lives into its own file inside of src. Hence, for the simple.vs design, you simply need to call:

$ make wave.simple

This will verilate the SystemVerilog file, compile the resulting C++ code together with its corresponding simulation from the sim directory, and launch GTKWave for the resulting wave file.

After you are done with all of this, simply call make clean and go touch some grass.

License

Released under the GPLv3+, Copyright (C) 2024-Ω Miquel Sabaté Solà.