GitHub - nrs14/VLSI-Verilog-code: verilog

Name		Name	Last commit message	Last commit date
Latest commit History 16 Commits
1-4 DEMUX.v		1-4 DEMUX.v
4:1 mux.v		4:1 mux.v
D FLIPFLOP WITH ENABLE & RESET.v		D FLIPFLOP WITH ENABLE & RESET.v
D FLIPFLOP WITH RESET.v		D FLIPFLOP WITH RESET.v
D FLIPFLOP.v		D FLIPFLOP.v
alu.v		alu.v
down_counter.v		down_counter.v
fulladder .v		fulladder .v
half adder.v		half adder.v
pipo.v		pipo.v
piso.v		piso.v
ring_counter.v		ring_counter.v
sipo.v		sipo.v
siso.v		siso.v
up_counter.v		up_counter.v
up_down_counter.v		up_down_counter.v