The qspi_master module facilitates reading and writing to flash memory in both single and quad modes. It generates spi_clk with an adjustable division relative to the system clock and can detect rising and falling edges one cycle in advance. Data is shifted out on the falling edge and sampled on the rising edge of spi_clk. To adhere to flash memory timing requirements, the module handles write operations by sending a sequence of command, address, and data, while read operations include command, address, and dummy cycles before sampling data. An FSM manages this sequence and uses a multiplexer to select between command, address, data, or dummy inputs based on the operation. The FSM also controls chip select (cs), enables spi_clk, and the transmitter or receiver depending on the operation. For high-speed transfers, quad mode uses 4 data lines when the appropriate control signal is asserted.

This module is verified with MT25QL128ABA qspi flash memory model in modelsim. The testbench provide stimuli to test write and read in quad mode.