QPMR header not found, unable to IPL #1
Comments
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Just as an experiment can you try using the hcode from hostboot-binaries? |
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@dcrowell77 We'd have to bring up a new build tree on a different server, as the HCODE build is integrated into our version of op-build. Also that won't help us with the demo, as one of the key points we're making is "this is running on full open source, no binary-only firmware components.". If it'll help narrow things down, I can try to run a test against the binary versions after the Summit. |
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@dcrowell77 One thing I did notice, picking through the HCODE binary versus the binary we generated, was that the internal versions in the two binaries don't line up at all. The binary-only version is "hw022318a.911", while the source version on GitHub is "hw030918a.910". Without access to the internal HCODE tree I have no way to know if a breaking change was implemented after "hw022318a.911". |
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I can tell you that hw022318a.911 is at 46c42b6f3bbf59bfa28d1231d4ef383f375fa28c but it looks like the commit numbers aren't quite matching up... (obviously still working out some kinks here). commit 46c42b6f3bbf59bfa28d1231d4ef383f375fa28c |
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It looks like the version of hcode that made its way up to github is missing some support for DD2.2. @jahunsbe is working on making and testing a fix now. |
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as a quick test you could update tools/build/rules.dir/chips.env.mk in the hcode repo |
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@dcrowell77, @rjknight With some adjustments for the Talos plaforms, we can now IPL on DD2.2. There are some new issues that have appeared (probably due to the hostboot, etc. updates required), most notably open-power/op-build#1974, but at least this is a good starting point. Thanks all for tracking that down so quickly! |
track pervasive scan region and SCOM ring hookups based on drop R VHDL and current Clock Voltage spec XLS match scan region updates FSI added fsi0inv (region #5) TP added dpllpau (region #8), dpllnest (region #9) N0 shifted pe1 to own region (region #4), added iopsi (region #6) N1 remove region #1 (mcd -> region #2, pe0 -> region #4) PCI add pcs0..3 (region #2-#5), psm0..3 (region #6-#9) MC remove region #2 (dl01 -> region #3, dl23 -> region #4, ioo0 -> region #5, ioo1 -> region #6) EQ added clkadj (region #10) AXON remove odl (region #3) match scom ring updates NMMU extend match to second SCOM satellite (#1) on ring #3 PEC,PHB correct n0/n1 instance numbering cover additional sat IDs (#4-#6) on PCI chiplet ring #2 PAUC rename from PPE remove non-IO PPE entries, P10 target will only cover IO PPEs add PTL, IO PPE matching rules (direct and per-bus indirect) support match for PAU chiplet pervasive resources PAU update ring matching rules (#2,#3 for first pau unit in chiplet, #4,#5 for second) IOHS limit ring match for direct AXON chiplet access to ring #4 (pdl) update matching rules for indirect PAU chiplet access via IOPPE, remove rules matching direct PAU chiplet access EQ fix matching rules for EQ,C target split of ring space on PSCOM endpoint #1 MC,MI adjust ring ID (mc_0 shifted from #2 to #3) change satellite ID matches to cover MCBIST and PBI MCC adjust ring ID (mc_0 shifted from #2 to #3), cover upstream and downstream TL layer registers as well as MCBIST/PBI indirect access to the channel facilities OMIC add matches for IO PPE indirect per-group regs, MC direct access through omi rings (#5-#6) for shared DL regs OMI add matches for IO PPE indirect per-lane regs, MC direct access through omi rings (#5-#6) for sub-channel specific DL regs (separate range for non PM and PM specific regs) update HWP metadata comments for scan xlate source files fix unitialized variables in p10_scom_xlate impacting clock domain analysis for chip target scoped input update unit test to cover matching changes Change-Id: I66ad0419be5b0915fef81769c82d9f3c3bbea768 Original-Change-Id: I769a4d76266ffcf94d803887e73c6acdf57e5107 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/76629 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Benjamin Gass <bgass@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
We're running into an issue on our Talos systems with DD2.2 and the latest hostboot / HCODE master trees. Our systems will not IPL, and throw errors in ISTEP 15 related to the QPMR header. Our internal diagnostics and @dcrowell77 are in agreement that the HCODE in this repository is either out of sync with the rest of the firmware, or simply broken.
Example output:
This is blocking our DD2.2 demos at the Summit. Migrated from open-power/hostboot#129
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