Fix RTC numbers for extra core state setup we do for MPIPL

There was a whole laundry list of scoms we were doing to the cores
to get the PM complex in the correct state for MPIPL. Many of these
workarounds have been removed but a few we could not. In order to move
forward I created new stories for the remaining workaround to remove
so we can close the previous story that contained all of the workaround

Change-Id: I66f02d867391afc22961a7de02b94293000607ae
RTC:171763
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/45983
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Elizabeth K. Liner <eliner@us.ibm.com>
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>

Author: crgeddes

src/usr/isteps/istep06/host_discover_targets.C

@@ -229,6 +229,7 @@ errlHndl_t clearInterruptReg()
 
     for(const auto & l_chip : l_procChips)
     {
+        //TODO 179645 Determine why we have to clear PERV_ATTN_INTERRUPT_REG during dump MPIPLs on DD2
         l_err = deviceWrite(l_chip,
                              &CLEAR_SCOM,
                              MASK_SIZE,
@@ -319,7 +320,7 @@ errlHndl_t powerDownSlaveQuads()
                                          TARGETING::TYPE_EX,
                                          true);
 
-            //TODO 171763 Core state setup for MPIPL should be done in a HWP
+            //TODO 171340 Need to rm clear of PM_EXIT bit in EX_0_CME_SCOM_SICR_SCOM1 reg during MPIPL
             for(const auto & l_ex_child : l_exChildren)
             {
                 // Clear bits 4 & 5 of CME_SCOM_SICR which sets PM_EXIT for C0 and C1 respectively