Fixes explorer RCD EFD byte swaps

The SPD for the explorer EFD RCD bytes are
already swapped into the microchip order.
As our code always swaps uint16_t's, we have to
swap the byte order when we go to read out the SPD bytes.

The original bug was found on the RCD DIC bytes.
The following 16-bit RCD bytes were checked
1. RCD DIC
2. RCD Voltage
3. RCD IBT CNTLR
4. RCD DB DIC
5. RCD Slew

Buts were found and fixed in:
1. RCD DIC
2. RCD Voltage
3. RCD Slew

Bugs were found by comparing the EFD ordering to the
attribute ordering to the microchip spec ordering.

(cherry picked from commit d0e2732d5f290d7c3efc1af68499be0b4e805089)

Change-Id: I750c98d8e40f7a9d6d6a2940e13c548f8f8189d6
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/106787
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Mark Pizzutillo <mark.pizzutillo@ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: Edgar R Cordero <ecordero@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/106812
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M Crowell <dcrowell@us.ibm.com>

Author: sglancy6

src/import/generic/memory/lib/spd/ddimm/ddr4/efd_ddr4_custom_microchip_decoder.H

@@ -1003,10 +1003,10 @@ class decoder<mss::spd::device_type::DDR4, DDR4_CUSTOM_MICROCHIP, R > : public b
         {
             uint8_t l_byte = 0;
 
-            // In the EFD, byte0 is the MSB and byte1 if the LSB
-            FAPI_TRY(( reader<fields_t::RCD_DIC_0, R>(iv_target, iv_data, l_byte)) );
-            o_output = l_byte << BITS_PER_BYTE;
+            // In the EFD, byte1 is the MSB and byte0 if the LSB
             FAPI_TRY(( reader<fields_t::RCD_DIC_1, R>(iv_target, iv_data, l_byte)) );
+            o_output = l_byte << BITS_PER_BYTE;
+            FAPI_TRY(( reader<fields_t::RCD_DIC_0, R>(iv_target, iv_data, l_byte)) );
             o_output |= l_byte;
             return fapi2::FAPI2_RC_SUCCESS;
 
@@ -1024,11 +1024,12 @@ class decoder<mss::spd::device_type::DDR4, DDR4_CUSTOM_MICROCHIP, R > : public b
         {
             uint8_t l_byte = 0;
 
-            // In the EFD, byte0 is the MSB and byte1 if the LSB
+            // In the EFD, we get bits 3:0 in byte 0 and 11:4 in byte 1
+            // We do a bit of shifting to get this to work out
             FAPI_TRY(( reader<fields_t::RCD_VOLTAGE_CTRL_0, R>(iv_target, iv_data, l_byte)) );
-            o_output = l_byte << BITS_PER_BYTE;
+            o_output = l_byte;
             FAPI_TRY(( reader<fields_t::RCD_VOLTAGE_CTRL_1, R>(iv_target, iv_data, l_byte)) );
-            o_output |= l_byte;
+            o_output |= (l_byte << BITS_PER_NIBBLE);
             return fapi2::FAPI2_RC_SUCCESS;
 
         fapi_try_exit:
@@ -1125,10 +1126,10 @@ class decoder<mss::spd::device_type::DDR4, DDR4_CUSTOM_MICROCHIP, R > : public b
         {
             uint8_t l_byte = 0;
 
-            // In the EFD, byte0 is the MSB and byte1 if the LSB
-            FAPI_TRY(( reader<fields_t::RCD_SLEW_RATE_CTRL_0, R>(iv_target, iv_data, l_byte)) );
-            o_output = l_byte << BITS_PER_BYTE;
+            // In the EFD, byte0 is the LSB and byte1 if the MSB
             FAPI_TRY(( reader<fields_t::RCD_SLEW_RATE_CTRL_1, R>(iv_target, iv_data, l_byte)) );
+            o_output = l_byte << BITS_PER_BYTE;
+            FAPI_TRY(( reader<fields_t::RCD_SLEW_RATE_CTRL_0, R>(iv_target, iv_data, l_byte)) );
             o_output |= l_byte;
             return fapi2::FAPI2_RC_SUCCESS;