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PMIC 4U - Add 4 new GPIO init steps
As defined in the 4U DDIMM Functional Spec V0.2 Change-Id: Ic8866b7f8f241ec553dd4213c7f05ddda7db6f7e Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/100959 Reviewed-by: Louis Stermole <stermole@us.ibm.com> Reviewed-by: Sneha Kadam <sneha.kadam@ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Dev-Ready: Mark Pizzutillo <mark.pizzutillo@ibm.com> Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Edgar R Cordero <ecordero@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/100975 Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Christian R Geddes <crgeddes@us.ibm.com>
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‎src/import/chips/ocmb/common/procedures/hwp/pmic/lib/utils/pmic_consts.H

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -377,6 +377,8 @@ namespace gpio
377377
enum regs
378378
{
379379
INPUT_PORT_REG = 0x00,
380+
EFUSE_OUTPUT = 0x01,
381+
EFUSE_POLARITY = 0x02,
380382
CONFIGURATION = 0x03,
381383
};
382384

@@ -388,6 +390,9 @@ enum fields
388390
INPUT_PORT_REG_PMIC_PAIR0 = 2,
389391
INPUT_PORT_REG_PMIC_PAIR1 = 3,
390392

393+
EFUSE_OUTPUT_SETTING = 0xFF,
394+
EFUSE_POLARITY_SETTING = 0x00,
395+
391396
// 1's are inputs, 0's are outputs
392397
CONFIGURATION_IO_MAP = 0xFC,
393398
};

‎src/import/chips/ocmb/common/procedures/hwp/pmic/lib/utils/pmic_enable_utils.C

Lines changed: 31 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -711,6 +711,35 @@ fapi_try_exit:
711711
return fapi2::current_err;
712712
}
713713

714+
///
715+
/// @brief Enable EFUSE according to 4U Functional Specification
716+
///
717+
/// @param[in] i_gpio GPIO target
718+
/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff success, else error code
719+
/// @note Corresponds to steps (6,7,8) & (16,17,18) in 4U DDIMM Functional Spec
720+
///
721+
fapi2::ReturnCode enable_efuse(const fapi2::Target<fapi2::TARGET_TYPE_GENERICI2CSLAVE>& i_gpio)
722+
{
723+
FAPI_DBG("Enabling EFUSE on %s", mss::c_str(i_gpio));
724+
fapi2::buffer<uint8_t> l_reg_contents;
725+
726+
// Step 6 / 16
727+
l_reg_contents = mss::gpio::fields::EFUSE_OUTPUT_SETTING;
728+
FAPI_TRY(mss::pmic::i2c::reg_write(i_gpio, mss::gpio::regs::EFUSE_OUTPUT, l_reg_contents));
729+
730+
// Step 7 / 17
731+
l_reg_contents = mss::gpio::fields::EFUSE_POLARITY_SETTING;
732+
FAPI_TRY(mss::pmic::i2c::reg_write(i_gpio, mss::gpio::regs::EFUSE_POLARITY, l_reg_contents));
733+
734+
// Step 8 / 18
735+
// Set pin to output type (this will turn on the E-Fuse)
736+
l_reg_contents = mss::gpio::fields::CONFIGURATION_IO_MAP;
737+
FAPI_TRY(mss::pmic::i2c::reg_write(i_gpio, mss::gpio::regs::CONFIGURATION, l_reg_contents));
738+
739+
fapi_try_exit:
740+
return fapi2::current_err;
741+
}
742+
714743
///
715744
/// @brief Set the up PMIC pair and matching GPIO expander prior to PMIC enable
716745
///
@@ -746,11 +775,8 @@ fapi2::ReturnCode setup_pmic_pair_and_gpio(
746775
FAPI_TRY(mss::pmic::validate_efuse_off(i_pmic0));
747776
FAPI_TRY(mss::pmic::validate_efuse_off(i_pmic1));
748777

749-
// Enable E-Fuse, set pin to output type (this will turn on the E-Fuse)
750-
FAPI_DBG("Enabling EFUSE on %s", mss::c_str(i_gpio));
751-
l_reg_contents.flush<0>();
752-
l_reg_contents = mss::gpio::fields::CONFIGURATION_IO_MAP;
753-
FAPI_TRY(mss::pmic::i2c::reg_write(i_gpio, mss::gpio::regs::CONFIGURATION, l_reg_contents));
778+
// Enable E-Fuse
779+
FAPI_TRY(enable_efuse(i_gpio));
754780

755781
// Delay 30ms looked consistantly good in testing
756782
fapi2::delay(30 * mss::common_timings::DELAY_1MS, mss::common_timings::DELAY_1MS);

‎src/import/chips/ocmb/common/procedures/hwp/pmic/lib/utils/pmic_enable_utils.H

Lines changed: 65 additions & 56 deletions
Original file line numberDiff line numberDiff line change
@@ -79,188 +79,188 @@ using ADC_FIELDS = mss::adc::fields;
7979
// pair<REG,DATA>
8080
static const std::vector<std::pair<uint8_t, uint8_t>> ADC1_CH_INIT =
8181
{
82-
// 29: Set channels to auto sequencing, all channels
82+
// 33: Set channels to auto sequencing, all channels
8383
{ADC_REGS::AUTO_SEQ_CH_SEL, ADC_FIELDS::AUTO_SEQ_CH_SEL_ALL_AUTO_SEQUENCING},
84-
// 30: Set auto sequence mode
84+
// 34: Set auto sequence mode
8585
{ADC_REGS::SEQUENCE_CFG, ADC_FIELDS::SEQUENCE_CFG_AUTO_SEQUENCE},
8686

8787
// CH 1
88-
// 31: Keep upper limit at max, enable hysteresis
88+
// 35: Keep upper limit at max, enable hysteresis
8989
{ADC_REGS::HYSTERESIS_CH1, ADC_FIELDS::HYSTERESIS_UPPER_LIMIT_MAX_ENABLE},
9090

91-
// 32: Keep default, may skip if not multibyte writing
91+
// 36: Keep default, may skip if not multibyte writing
9292
{ADC_REGS::HIGH_TH_CH1, ADC_FIELDS::HIGH_TH_DEFAULT},
9393

94-
// 33: Set up so alert must persist for 4 consecutive readings
94+
// 37: Set up so alert must persist for 4 consecutive readings
9595
{ADC_REGS::EVENT_COUNT_CH1, ADC_FIELDS::EVENT_COUNT_ADC1_CH1_ALERT_4_CONSECUTIVE_READINGS},
9696

97-
// 34: 1AB_VLOC (VDDR1) Low Threshold = 0.643 V
97+
// 38: 1AB_VLOC (VDDR1) Low Threshold = 0.643 V
9898
{ADC_REGS::LOW_TH_CH1, ADC_FIELDS::LOW_TH_CH1_1AB_VLOC_LOW_THRESHOLD_643mv},
9999

100100
// CH 2
101-
// 35: Keep upper limit at max, enable hysteresis
101+
// 39: Keep upper limit at max, enable hysteresis
102102
{ADC_REGS::HYSTERESIS_CH2, ADC_FIELDS::HYSTERESIS_UPPER_LIMIT_MAX_ENABLE},
103103

104-
// 36: Keep default, may skip if not multibyte writing
104+
// 40: Keep default, may skip if not multibyte writing
105105
{ADC_REGS::HIGH_TH_CH2, ADC_FIELDS::HIGH_TH_DEFAULT},
106106

107-
// 37: Set up so alert must persist for 4 consecutive readings
107+
// 41: Set up so alert must persist for 4 consecutive readings
108108
{ADC_REGS::EVENT_COUNT_CH2, ADC_FIELDS::EVENT_COUNT_ADC1_CH2_ALERT_4_CONSECUTIVE_READINGS},
109109

110-
// 38: 1C_VLOC (VIO) Low Threshold = 0.476 V
110+
// 42: 1C_VLOC (VIO) Low Threshold = 0.476 V
111111
{ADC_REGS::LOW_TH_CH2, ADC_FIELDS::LOW_TH_CH2_1C_VLOC_LOW_THRESHOLD_476mv},
112112

113113
// CH3
114-
// 39: Keep upper limit at max, enable hysteresis
114+
// 43: Keep upper limit at max, enable hysteresis
115115
{ADC_REGS::HYSTERESIS_CH3, ADC_FIELDS::HYSTERESIS_UPPER_LIMIT_MAX_ENABLE},
116116

117-
// 40: Keep default, may skip if not multibyte writing
117+
// 44: Keep default, may skip if not multibyte writing
118118
{ADC_REGS::HIGH_TH_CH3, ADC_FIELDS::HIGH_TH_DEFAULT},
119119

120-
// 41: Set up so alert must persist for 4 consecutive readings
120+
// 45: Set up so alert must persist for 4 consecutive readings
121121
{ADC_REGS::EVENT_COUNT_CH3, ADC_FIELDS::EVENT_COUNT_ADC1_CH3_ALERT_4_CONSECUTIVE_READINGS},
122122

123-
// 42: 1D_VLOC/2 (VPP) Low Threshold = 0.733 V
123+
// 46: 1D_VLOC/2 (VPP) Low Threshold = 0.733 V
124124
{ADC_REGS::LOW_TH_CH3, ADC_FIELDS::LOW_TH_CH3_1D_VLOC_LOW_THRESHOLD_733mv},
125125

126126
// CH 4
127-
// 43: Keep upper limit at max, enable hysteresis
127+
// 47: Keep upper limit at max, enable hysteresis
128128
{ADC_REGS::HYSTERESIS_CH4, ADC_FIELDS::HYSTERESIS_UPPER_LIMIT_MAX_ENABLE},
129129

130-
// 44: Keep default, may skip if not multibyte writing
130+
// 48: Keep default, may skip if not multibyte writing
131131
{ADC_REGS::HIGH_TH_CH4, ADC_FIELDS::HIGH_TH_DEFAULT},
132132

133-
// 45: Set up so alert must persist for 4 consecutive readings
133+
// 49: Set up so alert must persist for 4 consecutive readings
134134
{ADC_REGS::EVENT_COUNT_CH4, ADC_FIELDS::EVENT_COUNT_ADC1_CH4_ALERT_4_CONSECUTIVE_READINGS},
135135

136-
// 46: 2C_VLOC (VIO) Low Threshold = 0.476 V
136+
// 50: 2C_VLOC (VIO) Low Threshold = 0.476 V
137137
{ADC_REGS::LOW_TH_CH4, ADC_FIELDS::LOW_TH_CH4_2C_VLOC_LOW_THRESHOLD_476mv},
138138

139139
// CH 5
140-
// 47: Keep upper limit at max, enable hysteresis
140+
// 51: Keep upper limit at max, enable hysteresis
141141
{ADC_REGS::HYSTERESIS_CH5, ADC_FIELDS::HYSTERESIS_UPPER_LIMIT_MAX_ENABLE},
142142

143-
// 48: Keep default, may skip if not multibyte writing
143+
// 52: Keep default, may skip if not multibyte writing
144144
{ADC_REGS::HIGH_TH_CH5, ADC_FIELDS::HIGH_TH_DEFAULT},
145145

146-
// 49: Set up so alert must persist for 4 consecutive readings
146+
// 53: Set up so alert must persist for 4 consecutive readings
147147
{ADC_REGS::EVENT_COUNT_CH5, ADC_FIELDS::EVENT_COUNT_ADC1_CH5_ALERT_4_CONSECUTIVE_READINGS},
148148

149-
// 50: 2D_VLOC/2 (VPP) Low Threshold = 0.733 V
149+
// 54: 2D_VLOC/2 (VPP) Low Threshold = 0.733 V
150150
{ADC_REGS::LOW_TH_CH5, ADC_FIELDS::LOW_TH_CH5_2D_VLOC_LOW_THRESHOLD_733mv},
151151

152152
// CH 7
153-
// 51: Keep upper limit at max, enable hysteresis
153+
// 55: Keep upper limit at max, enable hysteresis
154154
{ADC_REGS::HYSTERESIS_CH7, ADC_FIELDS::HYSTERESIS_UPPER_LIMIT_MAX_ENABLE},
155155

156-
// 52: Keep default, may skip if not multibyte writing
156+
// 56: Keep default, may skip if not multibyte writing
157157
{ADC_REGS::HIGH_TH_CH7, ADC_FIELDS::HIGH_TH_DEFAULT},
158158

159-
// 53: Set up so alert must persist for 4 consecutive readings
159+
// 57: Set up so alert must persist for 4 consecutive readings
160160
{ADC_REGS::EVENT_COUNT_CH7, ADC_FIELDS::EVENT_COUNT_ADC1_CH7_ALERT_4_CONSECUTIVE_READINGS},
161161

162-
// 54: 2AB_VLOC Low (VDDR1) Threshold = 0.643 V
162+
// 58: 2AB_VLOC Low (VDDR1) Threshold = 0.643 V
163163
{ADC_REGS::LOW_TH_CH7, ADC_FIELDS::LOW_TH_CH7_2AB_VLOC_LOW_THRESHOLD_643mv},
164164

165165
// Finalize
166-
// 55: Set channels to trigger an alert, only local voltages
166+
// 59: Set channels to trigger an alert, only local voltages
167167
{ADC_REGS::ALERT_CH_SEL, ADC_FIELDS::ALERT_CH_SEL_ADC1_LOCAL_VOLTAGES_ALERT},
168168

169-
// 56: Set alert pin function to remain active high (not pulsed)
169+
// 60: Set alert pin function to remain active high (not pulsed)
170170
{ADC_REGS::ALERT_PIN_CFG, ADC_FIELDS::ALERT_PIN_CFG_ACTIVE_HIGH},
171171

172-
// 57: Setup autonomous conversions and sampling speed
172+
// 61: Setup autonomous conversions and sampling speed
173173
{ADC_REGS::OPMODE_CFG, ADC_FIELDS::OPMODE_CFG_AUTONOMOUS},
174174

175-
// 58: Set over sampling, 8 samples
175+
// 62: Set over sampling, 8 samples
176176
{ADC_REGS::OSR_CFG, ADC_FIELDS::OSR_CFG_8_SAMPLE_OVERSAMPLING},
177177

178-
// 59: Enable digital window comparator and stats
178+
// 63: Enable digital window comparator and stats
179179
{ADC_REGS::GENERAL_CFG, ADC_FIELDS::GENERAL_CFG_EN_DIGITAL_WINDOW_COMPARATOR_AND_STATS},
180180

181-
// 60: Enable Channel sequencing
181+
// 64: Enable Channel sequencing
182182
{ADC_REGS::SEQUENCE_CFG, ADC_FIELDS::SEQUENCE_CFG_CHANNEL_SEQUENCING}
183183
};
184184

185185
// ADC2 register sequence
186186
// pair<REG,DATA>
187187
static const std::vector<std::pair<uint8_t, uint8_t>> ADC2_CH_INIT =
188188
{
189-
// 61: Set channels to auto sequencing, all channels
189+
// 65: Set channels to auto sequencing, all channels
190190
{ADC_REGS::AUTO_SEQ_CH_SEL, ADC_FIELDS::AUTO_SEQ_CH_SEL_ALL_AUTO_SEQUENCING},
191191

192-
// 62: Set auto sequence mode
192+
// 66: Set auto sequence mode
193193
{ADC_REGS::SEQUENCE_CFG, ADC_FIELDS::SEQUENCE_CFG_AUTO_SEQUENCE},
194194

195195
// CH 2
196-
// 63: Keep upper limit at max, enable hysteresis
196+
// 67: Keep upper limit at max, enable hysteresis
197197
{ADC_REGS::HYSTERESIS_CH2, ADC_FIELDS::HYSTERESIS_UPPER_LIMIT_MAX_ENABLE},
198198

199-
// 64: Keep default, may skip if not multibyte writing
199+
// 68: Keep default, may skip if not multibyte writing
200200
{ADC_REGS::HIGH_TH_CH2, ADC_FIELDS::HIGH_TH_DEFAULT},
201201

202-
// 65: Set up so alert must persist for 4 consecutive readings
202+
// 69: Set up so alert must persist for 4 consecutive readings
203203
{ADC_REGS::EVENT_COUNT_CH2, ADC_FIELDS::EVENT_COUNT_ADC2_CH2_ALERT_4_CONSECUTIVE_READINGS},
204204

205-
// 66: 3C_VLOC (VDD) Low Threshold = 0.391 V
205+
// 70: 3C_VLOC (VDD) Low Threshold = 0.391 V
206206
{ADC_REGS::LOW_TH_CH2, ADC_FIELDS::LOW_TH_CH2_3C_VLOC_LOW_THRESHOLD_391mv},
207207

208208
// CH 3
209-
// 67: Keep upper limit at max, enable hysteresis
209+
// 71: Keep upper limit at max, enable hysteresis
210210
{ADC_REGS::HYSTERESIS_CH3, ADC_FIELDS::HYSTERESIS_UPPER_LIMIT_MAX_ENABLE},
211211

212-
// 68: Keep default, may skip if not multibyte writing
212+
// 72: Keep default, may skip if not multibyte writing
213213
{ADC_REGS::HIGH_TH_CH3, ADC_FIELDS::HIGH_TH_DEFAULT},
214214

215-
// 69: Set up so alert must persist for 4 consecutive readings
215+
// 73: Set up so alert must persist for 4 consecutive readings
216216
{ADC_REGS::EVENT_COUNT_CH3, ADC_FIELDS::EVENT_COUNT_ADC2_CH3_ALERT_4_CONSECUTIVE_READINGS},
217217

218-
// 70: 4AB_VLOC (VDDR2) Low Threshold = 0.643 V
218+
// 74: 4AB_VLOC (VDDR2) Low Threshold = 0.643 V
219219
{ADC_REGS::LOW_TH_CH3, ADC_FIELDS::LOW_TH_CH3_4AB_VLOC_LOW_THRESHOLD_543mv},
220220

221221
// CH 5
222-
// 71: Keep upper limit at max, enable hysteresis
222+
// 75: Keep upper limit at max, enable hysteresis
223223
{ADC_REGS::HYSTERESIS_CH5, ADC_FIELDS::HYSTERESIS_UPPER_LIMIT_MAX_ENABLE},
224224

225-
// 72: Keep default, may skip if not multibyte writing
225+
// 76: Keep default, may skip if not multibyte writing
226226
{ADC_REGS::HIGH_TH_CH5, ADC_FIELDS::HIGH_TH_DEFAULT},
227227

228-
// 73: Set up so alert must persist for 4 consecutive readings
228+
// 77: Set up so alert must persist for 4 consecutive readings
229229
{ADC_REGS::EVENT_COUNT_CH5, ADC_FIELDS::EVENT_COUNT_ADC2_CH5_ALERT_4_CONSECUTIVE_READINGS},
230230

231-
// 74: 4C_VLOC (VDD) Low Threshold = 0.391 V
231+
// 78: 4C_VLOC (VDD) Low Threshold = 0.391 V
232232
{ADC_REGS::LOW_TH_CH5, ADC_FIELDS::LOW_TH_CH5_4C_VLOC_LOW_THRESHOLD_391mv},
233233

234234
// CH 7
235-
// 75: Keep upper limit at max, enable hysteresis
235+
// 79: Keep upper limit at max, enable hysteresis
236236
{ADC_REGS::HYSTERESIS_CH7, ADC_FIELDS::HYSTERESIS_UPPER_LIMIT_MAX_ENABLE},
237237

238-
// 76: Keep default, may skip if not multibyte writing
238+
// 80: Keep default, may skip if not multibyte writing
239239
{ADC_REGS::HIGH_TH_CH7, ADC_FIELDS::HIGH_TH_DEFAULT},
240240

241-
// 77: Set up so alert must persist for 4 consecutive readings
241+
// 81: Set up so alert must persist for 4 consecutive readings
242242
{ADC_REGS::EVENT_COUNT_CH7, ADC_FIELDS::EVENT_COUNT_ADC2_CH7_ALERT_4_CONSECUTIVE_READINGS},
243243

244-
// 78: 3AB_VLOC (VDDR2) Low Threshold = 0.643 V
244+
// 82: 3AB_VLOC (VDDR2) Low Threshold = 0.643 V
245245
{ADC_REGS::LOW_TH_CH7, ADC_FIELDS::LOW_TH_CH7_3AB_VLOC_LOW_THRESHOLD_543mv},
246246

247247
// Finalize
248-
// 79: Set channels to trigger an alert, only local voltages
248+
// 83: Set channels to trigger an alert, only local voltages
249249
{ADC_REGS::ALERT_CH_SEL, ADC_FIELDS::ALERT_CH_SEL_ADC2_LOCAL_VOLTAGES_ALERT},
250250

251-
// 80: Set alert pin function to remain active high (not pulsed)
251+
// 84: Set alert pin function to remain active high (not pulsed)
252252
{ADC_REGS::ALERT_PIN_CFG, ADC_FIELDS::ALERT_PIN_CFG_ACTIVE_HIGH},
253253

254-
// 81: Setup autonomous conversions and sampling speed
254+
// 85: Setup autonomous conversions and sampling speed
255255
{ADC_REGS::OPMODE_CFG, ADC_FIELDS::OPMODE_CFG_AUTONOMOUS},
256256

257-
// 82: Set over sampling, 8 samples
257+
// 86: Set over sampling, 8 samples
258258
{ADC_REGS::OSR_CFG, ADC_FIELDS::OSR_CFG_8_SAMPLE_OVERSAMPLING},
259259

260-
// 83: Enable digital window comparator and stats
260+
// 87: Enable digital window comparator and stats
261261
{ADC_REGS::GENERAL_CFG, ADC_FIELDS::GENERAL_CFG_EN_DIGITAL_WINDOW_COMPARATOR_AND_STATS},
262262

263-
// 84: Enable Channel sequencing
263+
// 88: Enable Channel sequencing
264264
{ADC_REGS::SEQUENCE_CFG, ADC_FIELDS::SEQUENCE_CFG_CHANNEL_SEQUENCING}
265265
};
266266

@@ -691,6 +691,15 @@ fapi2::ReturnCode validate_efuse_off(const fapi2::Target<fapi2::TARGET_TYPE_PMIC
691691
///
692692
fapi2::ReturnCode validate_efuse_on(const fapi2::Target<fapi2::TARGET_TYPE_PMIC>& i_pmic_target);
693693

694+
///
695+
/// @brief Enable EFUSE according to 4U Functional Specification
696+
///
697+
/// @param[in] i_gpio GPIO target
698+
/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff success, else error code
699+
/// @note Corresponds to steps (6,7,8) & (16,17,18) in 4U DDIMM Functional Spec
700+
///
701+
fapi2::ReturnCode enable_efuse(const fapi2::Target<fapi2::TARGET_TYPE_GENERICI2CSLAVE>& i_gpio);
702+
694703
///
695704
/// @brief Set the up PMIC pair and matching GPIO expander prior to PMIC enable
696705
///

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