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CORE-V Family of RISC-V Cores
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README.md Updated link to CV32E40P Feb 11, 2020

README.md

core-v-cores

CORE-V Family of Open Source RISC-V Cores

Here are the links to the OpenHW Group CORE-V Family of RISC-V cores:

CV32E40P Originally known as the PULP RI5CY core, the CORE-V CV32 is a 32bit, 4-stage core that implements, RV32IMFCXpulp, has an optional 32-bit FPU supporting the F extension and instruction set extensions for DSP operations, including hardware loops, SIMD extensions, bit manipulation and post-increment instructions. This repository is has been moved (not forked) from the original PULP Platform github repository to its new home at the OpenHW Group github repository.

CV64A Originally known as the PULP Ariane core, the CORE-V CV64 is a 64bit, 6-stage, single issue, in-order core implementing RV64GC extensions with three privilege levels M, S, U to fully support a Unix-like (Linux, BSD, etc.) operating system. It has configurable size, separate TLBs, a hardware PTW and branch-prediction (branch target buffer, branch history table and a return address stack). This repository is currently located in the PULP Platform github repositories and will be moved to the OpenHW Group github repositories in the coming weeks.

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