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Expand uDMA memory map #285

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merged 6 commits into from
Jan 12, 2023
Merged

Expand uDMA memory map #285

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5733709
Fix bullets
MikeOpenHWGroup Jan 10, 2023
5250da9
Resolve PDF generation errors and HTML generation warnings
MikeOpenHWGroup Jan 10, 2023
b396696
Specify specifc sphinx version
MikeOpenHWGroup Jan 10, 2023
3f84c18
Merge branch 'openhwgroup:master' into master
MikeOpenHWGroup Jan 11, 2023
9b68037
Merge branch 'openhwgroup:master' into master
MikeOpenHWGroup Jan 11, 2023
b067a20
Expand uDMA peripheral addressing
MikeOpenHWGroup Jan 12, 2023
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5 changes: 4 additions & 1 deletion docs/conf.py
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Original file line number Diff line number Diff line change
@@ -1,3 +1,7 @@
# Copyright 2022 OpenHW Group
# Solderpad Hardware License, Version 2.1, see LICENSE.md for details.
# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1

# Configuration file for the Sphinx documentation builder.
#
# This file only contains a selection of the most common options. For a full
Expand Down Expand Up @@ -30,7 +34,6 @@
extensions = [
'recommonmark',
'sphinx_markdown_tables',
# 'sphinx.ext.autosectionlabel',
]
# Add any paths that contain templates here, relative to this directory.
templates_path = ['_templates']
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50 changes: 32 additions & 18 deletions docs/doc-src/mmap.rst
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Expand Up @@ -29,47 +29,61 @@ The interleaved memory is typically used for program data-store and micro-DMA da
+-----------------------------------+--------------------+------------------+
| **Description** | **Address Start** | **Address End** |
+===================================+====================+==================+
| **Boot ROM** | 0x1A00-0000 | 0x1A03-FFFF |
| Boot ROM** | 0x1A00-0000 | 0x1A03-FFFF |
+-----------------------------------+--------------------+------------------+
| **Peripheral Domain** | 0x1A10-0000 | 0x1A2F-FFFF |
| Peripheral Domain | 0x1A10-0000 | 0x1A2F-FFFF |
+-----------------------------------+--------------------+------------------+
| **eFPGA Domain** | 0x1A30-0000 | 0x1A3F-FFFF |
| eFPGA Domain | 0x1A30-0000 | 0x1A3F-FFFF |
+-----------------------------------+--------------------+------------------+
| **Non-Interleaved Memory Bank 0** | 0x1C00-0000 | 0x1C00-7FFF |
| Non-Interleaved Memory Bank 0 | 0x1C00-0000 | 0x1C00-7FFF |
+-----------------------------------+--------------------+------------------+
| **Non-Interleaved Memory Bank 1** | 0x1C00-8000 | 0x1C00-FFFF |
| Non-Interleaved Memory Bank 1 | 0x1C00-8000 | 0x1C00-FFFF |
+-----------------------------------+--------------------+------------------+
| **Interleaved Memory** | 0x1C010000 | 0x1C07FFFF |
| Interleaved Memory | 0x1C010000 | 0x1C07FFFF |
+-----------------------------------+--------------------+------------------+

Memory locations in the peripheral domain are used to access Control and Status Registers (CSRs) used to control the CORE-V-MCU IP blocks.

+-----------------------------+---------------------------+---------------------------+
| **CORE-V-MCU IP Block** | **Address Start** | **Address End** |
+=============================+===========================+===========================+
| **Frequency-locked loop** | 0x1A100000 | 0x1A100FFF |
| APB Frequency-locked loop | 0x1A10-0000 | 0x1A10-0FFC |
+-----------------------------+---------------------------+---------------------------+
| **GPIOs** | 0x1A101000 | 0x1A101FFF |
| APB GPIOs | 0x1A10-1000 | 0x1A10-1FFC |
+-----------------------------+---------------------------+---------------------------+
| **uDMA** | 0x1A102000 | 0x1A103FFF |
| uDMA | 0x1A10-2000 | 0x1A10-3FFC |
+-----------------------------+---------------------------+---------------------------+
| **SoC Controller** | 0x1A104000 | 0x1A104FFF |
| uDMA UART0 | 0x1A10-2080 | 0x1A10-20FC |
+-----------------------------+---------------------------+---------------------------+
| **Advanced Timer** | 0x1A105000 | 0x1A105FFF |
| uDMA UART1 | 0x1A10-2100 | 0x1A10-217C |
+-----------------------------+---------------------------+---------------------------+
| **SoC Event Generator** | 0x1A106000 | 0x1A106FFF |
| uDMA QSPI0 | 0x1A10-2180 | 0x1A10-21FC |
+-----------------------------+---------------------------+---------------------------+
| **I2CS** | 0x1A107000 | 0x1A107FFF |
| uDMA QSPI1 | 0x1A10-2200 | 0x1A10-227C |
+-----------------------------+---------------------------+---------------------------+
| **Timer** | 0x1A10B000 | 0x1A10BFFF |
| uDMA I2CM0 | 0x1A10-2280 | 0x1A10-22FC |
+-----------------------------+---------------------------+---------------------------+
| **stdout emulator** | 0x1A10-F000 | 0x1A10-FFFF |
| uDMA I2CM1 | 0x1A10-2300 | 0x1A10-237C |
+-----------------------------+---------------------------+---------------------------+
| **Debug** | 0x1A11-0000 | 0x1A11-FFFF |
| uDMA SDIO | 0x1A10-2380 | 0x1A10-23FC |
+-----------------------------+---------------------------+---------------------------+
| **eFPGA configuration** | 0x1A200000 | 0x1A2F0000 |
| uDMA CAMERA | 0x1A10-2400 | 0x1A10-247C |
+-----------------------------+---------------------------+---------------------------+
| **eFPGA HWCE** | 0x1A300000 | 0x1A3F0000 |
| APB SoC Controller | 0x1A10-4000 | 0x1A10-4FFC |
+-----------------------------+---------------------------+---------------------------+
| APB Advanced Timer | 0x1A10-5000 | 0x1A10-5FFC |
+-----------------------------+---------------------------+---------------------------+
| APB SoC Event Controller | 0x1A10-6000 | 0x1A10-6FFC |
+-----------------------------+---------------------------+---------------------------+
| APB I2CS | 0x1A10-7000 | 0x1A10-7FFC |
+-----------------------------+---------------------------+---------------------------+
| APB Timer | 0x1A10-B000 | 0x1A10-BFFC |
+-----------------------------+---------------------------+---------------------------+
| stdout emulator | 0x1A10-F000 | 0x1A10-FFFC |
+-----------------------------+---------------------------+---------------------------+
| Debug | 0x1A11-0000 | 0x1A11-FFFC |
+-----------------------------+---------------------------+---------------------------+
| eFPGA configuration | 0x1A20-0000 | 0x1A2F-0000 |
+-----------------------------+---------------------------+---------------------------+

Note that the stdout emulator works only with RTL simulation and not with FPGA or ASIC implementations.
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37 changes: 12 additions & 25 deletions docs/doc-src/udma_subsystem.rst
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Expand Up @@ -144,32 +144,16 @@ The first 128*15 bytes are dedicated to the 15 peripherals while the last 32 con

uDMA Subsystem CSRs
-------------------
The UDMA addresses are organized as an array of channels.
The first channel, channel 0, is a control channel that is used to:
The uDMA implements three CSRs to:

* enable or disable the peripheral clocks
* set compare value for the event matching mechanism
* reset the periperal controller
* set compare value for the event macthing mechanism

The base address for the UDMA channels is defined as UDMA_START_ADDR in core-v-mcu-config.h
The size of each channel is UDMA_CH_SIZE, therefore the address of channels N is UDMA_START_ADDR+N*UDMA_CH_SIZE.
core-v-mcu-config.h has explicit defines for each peripheral.
For instance, if there are 2 UARTS then there are three defines:
These uDMA CSRs are defined below.

* UDMA_CH_ADDR_UART -- address of first UART
* UDMA_CH_ADDR_UART0 -- address of UART0
* UDMA_CH_ADDR_UART1 -- address of UART1

The reason for having the UDMA_CH_UART define
is so that you can programmatically access UART ID by using
UDMA_CH_ADDR_UART + ID * UDMA_CH_SIZE

The register definitions for the control channel are specified in this section.
The register definitions for each peripheral are specified in sections named UDMA_XXXXX.


REG_CG offset = 0x000
~~~~~~~~~~~~~~~~~~~~~
UDMA_CLK_EN offset = 0x000
~~~~~~~~~~~~~~~~~~~~~~~~~~

+-------------------+-------+------+------------+-------------------------------------------------------------------------+
| Field | Bits | Type | Default | Description |
Expand All @@ -179,8 +163,8 @@ REG_CG offset = 0x000
| | see core-v-mcu_config 'Peripheral clock enable masks' for bit positions |
+-------------------+-------+------+------------+-------------------------------------------------------------------------+

REG_CFG_EVT offset = 0x004
~~~~~~~~~~~~~~~~~~~~~~~~~~
UDMA_CFG_EVT offset = 0x004
~~~~~~~~~~~~~~~~~~~~~~~~~~~

+------------+-------+------+------------+-------------------------------------------------------------+
| Field | Bits | Type | Default | Description |
Expand All @@ -194,8 +178,8 @@ REG_CFG_EVT offset = 0x004
| CMP_EVENT0 | 7:0 | | 0x03 | Compare value for event detection |
+------------+-------+------+------------+-------------------------------------------------------------+

REG_RST offset = 0x008
~~~~~~~~~~~~~~~~~~~~~~
UDMA_RST offset = 0x008
~~~~~~~~~~~~~~~~~~~~~~~

+--------------+-------+------+------------+-------------------------------------------------------------------------+
| Field | Bits | Type | Default | Description |
Expand All @@ -205,3 +189,6 @@ REG_RST offset = 0x008
| | use core-v-mcu_config 'Peripheral clock enable masks' for bit positions |
+--------------+-------+------+------------+-------------------------------------------------------------------------+

.. note::
Most of the CSRs associated with the Micro-DMA are actually uDMA peripheral CSRs.
While the uDMA subsystem implements the selection logic for uDMA peripheral CSRs, this is transparent to the user.
4 changes: 2 additions & 2 deletions docs/requirements.txt
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Expand Up @@ -3,6 +3,6 @@
# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1

recommonmark
sphinx
sphinx>=4.3.0
sphinx_markdown_tables
sphinx_rtd_theme
sphinx_rtd_theme>=0.5.1