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8294492: RISC-V: Use li instead of patchable movptr at non-patchable callsites #10462

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8294492: RISC-V: Use li instead of patchable movptr at non-patchable callsites #10462

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ba3cfab
Change Non-patchable movptr to li, for movptr is defined implicitly f…
zhengxiaolinX Sep 28, 2022
d58e2a7
Further cleanup
zhengxiaolinX Sep 28, 2022
62cf62c
Further
zhengxiaolinX Sep 28, 2022
ad15d6b
Fix
zhengxiaolinX Sep 28, 2022
4985dcf
Fix as to comments
zhengxiaolinX Sep 28, 2022
60608a3
Comments, with one &
zhengxiaolinX Sep 28, 2022
fe56ee0
Canonicalize signed extensions
zhengxiaolinX Sep 28, 2022
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26 changes: 0 additions & 26 deletions src/hotspot/cpu/riscv/assembler_riscv.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -187,30 +187,6 @@ void Assembler::li32(Register Rd, int32_t imm) {

#undef INSN

void Assembler::ret() {
jalr(x0, x1, 0);
}

#define INSN(NAME, REGISTER) \
void Assembler::NAME(const address &dest, Register temp) { \
assert_cond(dest != NULL); \
assert(temp != noreg, "temp must not be empty register!"); \
int64_t distance = dest - pc(); \
if (is_offset_in_range(distance, 32)) { \
auipc(temp, distance + 0x800); \
jalr(REGISTER, temp, ((int32_t)distance << 20) >> 20); \
} else { \
int32_t offset = 0; \
movptr(temp, dest, offset); \
jalr(REGISTER, temp, offset); \
} \
}

INSN(call, x1);
INSN(tail, x0);

#undef INSN

#define INSN(NAME, REGISTER) \
void Assembler::NAME(const Address &adr, Register temp) { \
switch (adr.getMode()) { \
Expand All @@ -232,8 +208,6 @@ void Assembler::ret() {

INSN(j, x0);
INSN(jal, x1);
INSN(call, x1);
INSN(tail, x0);

#undef INSN

Expand Down
14 changes: 2 additions & 12 deletions src/hotspot/cpu/riscv/assembler_riscv.hpp
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Original file line number Diff line number Diff line change
Expand Up @@ -302,7 +302,8 @@ class Assembler : public AbstractAssembler {
lui(Rd, upper);
offset = lower;
} else {
movptr(Rd, (address)(uintptr_t)adr.offset(), offset);
offset = ((int32_t)adr.offset() << 20) >> 20;
li(Rd, adr.offset() - offset);
}
add(Rd, Rd, adr.base());
}
Expand Down Expand Up @@ -331,17 +332,6 @@ class Assembler : public AbstractAssembler {
void jal(const Address &adr, Register temp = t0);
void jr(Register Rs);
void jalr(Register Rs);
void ret();
void call(const address &dest, Register temp = t0);
void call(const Address &adr, Register temp = t0);
void tail(const address &dest, Register temp = t0);
void tail(const Address &adr, Register temp = t0);
void call(Label &l, Register temp) {
call(target(l), temp);
}
void tail(Label &l, Register temp) {
tail(target(l), temp);
}

static inline uint32_t extract(uint32_t val, unsigned msb, unsigned lsb) {
assert_cond(msb >= lsb && msb <= 31);
Expand Down
28 changes: 15 additions & 13 deletions src/hotspot/cpu/riscv/gc/shenandoah/shenandoahBarrierSetAssembler_riscv.cpp
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Expand Up @@ -282,24 +282,25 @@ void ShenandoahBarrierSetAssembler::load_reference_barrier(MacroAssembler* masm,
}

__ push_call_clobbered_registers();
address target = NULL;
if (is_strong) {
if (is_narrow) {
__ mv(ra, CAST_FROM_FN_PTR(address, ShenandoahRuntime::load_reference_barrier_strong_narrow));
target = CAST_FROM_FN_PTR(address, ShenandoahRuntime::load_reference_barrier_strong_narrow);
} else {
__ mv(ra, CAST_FROM_FN_PTR(address, ShenandoahRuntime::load_reference_barrier_strong));
target = CAST_FROM_FN_PTR(address, ShenandoahRuntime::load_reference_barrier_strong);
}
} else if (is_weak) {
if (is_narrow) {
__ mv(ra, CAST_FROM_FN_PTR(address, ShenandoahRuntime::load_reference_barrier_weak_narrow));
target = CAST_FROM_FN_PTR(address, ShenandoahRuntime::load_reference_barrier_weak_narrow);
} else {
__ mv(ra, CAST_FROM_FN_PTR(address, ShenandoahRuntime::load_reference_barrier_weak));
target = CAST_FROM_FN_PTR(address, ShenandoahRuntime::load_reference_barrier_weak);
}
} else {
assert(is_phantom, "only remaining strength");
assert(!is_narrow, "phantom access cannot be narrow");
__ mv(ra, CAST_FROM_FN_PTR(address, ShenandoahRuntime::load_reference_barrier_weak));
target = CAST_FROM_FN_PTR(address, ShenandoahRuntime::load_reference_barrier_weak);
}
__ jalr(ra);
__ call(target);
__ mv(t0, x10);
__ pop_call_clobbered_registers();
__ mv(x10, t0);
Expand Down Expand Up @@ -679,29 +680,30 @@ void ShenandoahBarrierSetAssembler::generate_c1_load_reference_barrier_runtime_s
bool is_weak = ShenandoahBarrierSet::is_weak_access(decorators);
bool is_phantom = ShenandoahBarrierSet::is_phantom_access(decorators);
bool is_native = ShenandoahBarrierSet::is_native_access(decorators);
address target = NULL;
if (is_strong) {
if (is_native) {
__ mv(ra, CAST_FROM_FN_PTR(address, ShenandoahRuntime::load_reference_barrier_strong));
target = CAST_FROM_FN_PTR(address, ShenandoahRuntime::load_reference_barrier_strong);
} else {
if (UseCompressedOops) {
__ mv(ra, CAST_FROM_FN_PTR(address, ShenandoahRuntime::load_reference_barrier_strong_narrow));
target = CAST_FROM_FN_PTR(address, ShenandoahRuntime::load_reference_barrier_strong_narrow);
} else {
__ mv(ra, CAST_FROM_FN_PTR(address, ShenandoahRuntime::load_reference_barrier_strong));
target = CAST_FROM_FN_PTR(address, ShenandoahRuntime::load_reference_barrier_strong);
}
}
} else if (is_weak) {
assert(!is_native, "weak must not be called off-heap");
if (UseCompressedOops) {
__ mv(ra, CAST_FROM_FN_PTR(address, ShenandoahRuntime::load_reference_barrier_weak_narrow));
target = CAST_FROM_FN_PTR(address, ShenandoahRuntime::load_reference_barrier_weak_narrow);
} else {
__ mv(ra, CAST_FROM_FN_PTR(address, ShenandoahRuntime::load_reference_barrier_weak));
target = CAST_FROM_FN_PTR(address, ShenandoahRuntime::load_reference_barrier_weak);
}
} else {
assert(is_phantom, "only remaining strength");
assert(is_native, "phantom must only be called off-heap");
__ mv(ra, CAST_FROM_FN_PTR(address, ShenandoahRuntime::load_reference_barrier_phantom));
target = CAST_FROM_FN_PTR(address, ShenandoahRuntime::load_reference_barrier_phantom);
}
__ jalr(ra);
__ call(target);
__ mv(t0, x10);
__ pop_call_clobbered_registers();
__ mv(x10, t0);
Expand Down
4 changes: 1 addition & 3 deletions src/hotspot/cpu/riscv/macroAssembler_riscv.cpp
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Expand Up @@ -563,10 +563,8 @@ void MacroAssembler::emit_static_call_stub() {
void MacroAssembler::call_VM_leaf_base(address entry_point,
int number_of_arguments,
Label *retaddr) {
int32_t offset = 0;
push_reg(RegSet::of(t0, xmethod), sp); // push << t0 & xmethod >> to sp
movptr(t0, entry_point, offset);
jalr(x1, t0, offset);
call(entry_point);
if (retaddr != NULL) {
bind(*retaddr);
}
Expand Down
24 changes: 21 additions & 3 deletions src/hotspot/cpu/riscv/macroAssembler_riscv.hpp
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Expand Up @@ -527,12 +527,18 @@ class MacroAssembler: public Assembler {
}

// mv
void mv(Register Rd, address addr) { li(Rd, (int64_t)addr); }
void mv(Register Rd, address addr) { li(Rd, (int64_t)addr); }
void mv(Register Rd, address addr, int32_t &offset) {
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@RealFYang RealFYang Sep 28, 2022 •
edited
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We should add necessary comment for this function, like:
"Split address into a lower 12-bit sign-extended offset and the remainder so that the offset could be encoded in jalr or load/store instruction."

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done - added.

// Split address into a lower 12-bit sign-extended offset and the remainder,
// so that the offset could be encoded in jalr or load/store instruction.
offset = ((int32_t)(int64_t)addr << 20) >> 20;
li(Rd, (int64_t)addr - offset);
}

template<typename T, ENABLE_IF(std::is_integral<T>::value)>
inline void mv(Register Rd, T o) { li(Rd, (int64_t)o); }
inline void mv(Register Rd, T o) { li(Rd, (int64_t)o); }

inline void mvw(Register Rd, int32_t imm32) { mv(Rd, imm32); }
inline void mvw(Register Rd, int32_t imm32) { mv(Rd, imm32); }

void mv(Register Rd, Address dest);
void mv(Register Rd, RegisterOrConstant src);
Expand Down Expand Up @@ -890,6 +896,18 @@ class MacroAssembler: public Assembler {

void rt_call(address dest, Register tmp = t0);

void call(const address dest, Register temp = t0) {
assert_cond(dest != NULL);
assert(temp != noreg, "temp must not be empty register!");
int32_t offset = 0;
mv(temp, dest, offset);
jalr(x1, temp, offset);
}

void ret() {
jalr(x0, x1, 0);
}

private:

#ifdef ASSERT
Expand Down
8 changes: 2 additions & 6 deletions src/hotspot/cpu/riscv/stubGenerator_riscv.cpp
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Expand Up @@ -651,9 +651,7 @@ class StubGenerator: public StubCodeGenerator {
assert(frame::arg_reg_save_area_bytes == 0, "not expecting frame reg save area");
#endif
BLOCK_COMMENT("call MacroAssembler::debug");
int32_t offset = 0;
__ movptr(t0, CAST_FROM_FN_PTR(address, MacroAssembler::debug64), offset);
__ jalr(x1, t0, offset);
__ call(CAST_FROM_FN_PTR(address, MacroAssembler::debug64));
__ ebreak();

return start;
Expand Down Expand Up @@ -3740,9 +3738,7 @@ class StubGenerator: public StubCodeGenerator {
}
__ mv(c_rarg0, xthread);
BLOCK_COMMENT("call runtime_entry");
int32_t offset = 0;
__ movptr(t0, runtime_entry, offset);
__ jalr(x1, t0, offset);
__ call(runtime_entry);

// Generate oop map
OopMap* map = new OopMap(framesize, 0);
Expand Down
27 changes: 9 additions & 18 deletions src/hotspot/cpu/riscv/templateInterpreterGenerator_riscv.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -190,8 +190,7 @@ address TemplateInterpreterGenerator::generate_math_entry(AbstractInterpreter::M
} else {
fn = CAST_FROM_FN_PTR(address, StubRoutines::dsin());
}
__ mv(t0, fn);
__ jalr(t0);
__ call(fn);
break;
case Interpreter::java_lang_math_cos :
entry_point = __ pc();
Expand All @@ -204,8 +203,7 @@ address TemplateInterpreterGenerator::generate_math_entry(AbstractInterpreter::M
} else {
fn = CAST_FROM_FN_PTR(address, StubRoutines::dcos());
}
__ mv(t0, fn);
__ jalr(t0);
__ call(fn);
break;
case Interpreter::java_lang_math_tan :
entry_point = __ pc();
Expand All @@ -218,8 +216,7 @@ address TemplateInterpreterGenerator::generate_math_entry(AbstractInterpreter::M
} else {
fn = CAST_FROM_FN_PTR(address, StubRoutines::dtan());
}
__ mv(t0, fn);
__ jalr(t0);
__ call(fn);
break;
case Interpreter::java_lang_math_log :
entry_point = __ pc();
Expand All @@ -232,8 +229,7 @@ address TemplateInterpreterGenerator::generate_math_entry(AbstractInterpreter::M
} else {
fn = CAST_FROM_FN_PTR(address, StubRoutines::dlog());
}
__ mv(t0, fn);
__ jalr(t0);
__ call(fn);
break;
case Interpreter::java_lang_math_log10 :
entry_point = __ pc();
Expand All @@ -246,8 +242,7 @@ address TemplateInterpreterGenerator::generate_math_entry(AbstractInterpreter::M
} else {
fn = CAST_FROM_FN_PTR(address, StubRoutines::dlog10());
}
__ mv(t0, fn);
__ jalr(t0);
__ call(fn);
break;
case Interpreter::java_lang_math_exp :
entry_point = __ pc();
Expand All @@ -260,8 +255,7 @@ address TemplateInterpreterGenerator::generate_math_entry(AbstractInterpreter::M
} else {
fn = CAST_FROM_FN_PTR(address, StubRoutines::dexp());
}
__ mv(t0, fn);
__ jalr(t0);
__ call(fn);
break;
case Interpreter::java_lang_math_pow :
entry_point = __ pc();
Expand All @@ -275,8 +269,7 @@ address TemplateInterpreterGenerator::generate_math_entry(AbstractInterpreter::M
} else {
fn = CAST_FROM_FN_PTR(address, StubRoutines::dpow());
}
__ mv(t0, fn);
__ jalr(t0);
__ call(fn);
break;
case Interpreter::java_lang_math_fmaD :
if (UseFMA) {
Expand Down Expand Up @@ -1169,8 +1162,7 @@ address TemplateInterpreterGenerator::generate_native_entry(bool synchronized) {
// hand.
//
__ mv(c_rarg0, xthread);
__ mv(t1, CAST_FROM_FN_PTR(address, JavaThread::check_special_condition_for_native_trans));
__ jalr(t1);
__ call(CAST_FROM_FN_PTR(address, JavaThread::check_special_condition_for_native_trans));
__ get_method(xmethod);
__ reinit_heapbase();
__ bind(Continue);
Expand Down Expand Up @@ -1219,8 +1211,7 @@ address TemplateInterpreterGenerator::generate_native_entry(bool synchronized) {

__ push_call_clobbered_registers();
__ mv(c_rarg0, xthread);
__ mv(t1, CAST_FROM_FN_PTR(address, SharedRuntime::reguard_yellow_pages));
__ jalr(t1);
__ call(CAST_FROM_FN_PTR(address, SharedRuntime::reguard_yellow_pages));
__ pop_call_clobbered_registers();
__ bind(no_reguard);
}
Expand Down
2 changes: 1 addition & 1 deletion src/hotspot/cpu/riscv/templateTable_riscv.cpp
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Expand Up @@ -387,7 +387,7 @@ void TemplateTable::fast_aldc(bool wide) {

// Stash null_sentinel address to get its value later
int32_t offset = 0;
__ movptr(rarg, Universe::the_null_sentinel_addr(), offset);
__ mv(rarg, Universe::the_null_sentinel_addr(), offset);
__ ld(tmp, Address(rarg, offset));
__ resolve_oop_handle(tmp, x15, t1);
__ bne(result, tmp, notNull);
Expand Down