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8368724: RISC-V: Remove AvoidUnalignedAccesses Flag #27510

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3f657e0
RISC-V: Add unaligned access check
Anjian-Wen Sep 26, 2025
42f1db9
delete AvoidUnalignedAccesses and extra unnecessary check
Anjian-Wen Oct 10, 2025
910840d
Merge branch 'master' into add_unaligned_access_check
Anjian-Wen Oct 10, 2025
c1b209f
delete whitespace
Anjian-Wen Oct 10, 2025
be963cd
fix the use of unaligned_access
Anjian-Wen Oct 10, 2025
6eb1dd9
modify the global flag change
Anjian-Wen Oct 10, 2025
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26 changes: 13 additions & 13 deletions src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -502,7 +502,7 @@ void C2_MacroAssembler::string_indexof_char(Register str1, Register cnt1,

bind(DO_LONG);
mv(orig_cnt, cnt1);
if (AvoidUnalignedAccesses) {
if (!UseUnalignedAccesses) {
Label ALIGNED;
andi(unaligned_elems, str1, 0x7);
beqz(unaligned_elems, ALIGNED);
Expand Down Expand Up @@ -1012,7 +1012,7 @@ void C2_MacroAssembler::string_indexof_linearscan(Register haystack, Register ne
slli(tmp3, result_tmp, haystack_chr_shift); // result as tmp
add(haystack, haystack, tmp3);
neg(hlen_neg, tmp3);
if (AvoidUnalignedAccesses) {
if (!UseUnalignedAccesses) {
// preload first value, then we will read by 1 character per loop, instead of four
// just shifting previous ch2 right by size of character in bits
add(tmp3, haystack, hlen_neg);
Expand All @@ -1028,7 +1028,7 @@ void C2_MacroAssembler::string_indexof_linearscan(Register haystack, Register ne

bind(CH1_LOOP);
add(tmp3, haystack, hlen_neg);
if (AvoidUnalignedAccesses) {
if (!UseUnalignedAccesses) {
srli(ch2, ch2, isLL ? 8 : 16);
(this->*haystack_load_1chr)(tmp3, Address(tmp3, isLL ? 3 : 6), noreg);
slli(tmp3, tmp3, isLL ? 24 : 48);
Expand All @@ -1053,7 +1053,7 @@ void C2_MacroAssembler::string_indexof_linearscan(Register haystack, Register ne
slli(tmp3, result_tmp, haystack_chr_shift);
add(haystack, haystack, tmp3);
neg(hlen_neg, tmp3);
if (AvoidUnalignedAccesses) {
if (!UseUnalignedAccesses) {
// preload first value, then we will read by 1 character per loop, instead of two
// just shifting previous ch2 right by size of character in bits
add(tmp3, haystack, hlen_neg);
Expand All @@ -1062,7 +1062,7 @@ void C2_MacroAssembler::string_indexof_linearscan(Register haystack, Register ne
}
bind(CH1_LOOP);
add(tmp3, haystack, hlen_neg);
if (AvoidUnalignedAccesses) {
if (!UseUnalignedAccesses) {
srli(ch2, ch2, isLL ? 8 : 16);
(this->*haystack_load_1chr)(tmp3, Address(tmp3, isLL ? 1 : 2), noreg);
slli(tmp3, tmp3, isLL ? 8 : 16);
Expand Down Expand Up @@ -1093,7 +1093,7 @@ void C2_MacroAssembler::string_indexof_linearscan(Register haystack, Register ne

bind(FIRST_LOOP);
add(ch2, haystack, hlen_neg);
if (AvoidUnalignedAccesses) {
if (!UseUnalignedAccesses) {
(this->*haystack_load_1chr)(tmp2, Address(ch2, isLL ? 1 : 2), noreg); // we need a temp register, we can safely use hlen_tmp here, which is a synonym for tmp2
(this->*haystack_load_1chr)(ch2, Address(ch2), noreg);
slli(tmp2, tmp2, isLL ? 8 : 16);
Expand Down Expand Up @@ -1164,7 +1164,7 @@ void C2_MacroAssembler::string_compare_long_same_encoding(Register result, Regis
// load first parts of strings and finish initialization while loading
beq(str1, str2, *DONE);
// Alignment
if (AvoidUnalignedAccesses && (base_offset % 8) != 0) {
if (!UseUnalignedAccesses && (base_offset % 8) != 0) {
lwu(tmp1, Address(str1));
lwu(tmp2, Address(str2));
bne(tmp1, tmp2, DIFFERENCE);
Expand All @@ -1177,7 +1177,7 @@ void C2_MacroAssembler::string_compare_long_same_encoding(Register result, Regis
ble(cnt2, t0, *SHORT_STRING);
}
#ifdef ASSERT
if (AvoidUnalignedAccesses) {
if (!UseUnalignedAccesses) {
Label align_ok;
orr(t0, str1, str2);
andi(t0, t0, 0x7);
Expand Down Expand Up @@ -1206,7 +1206,7 @@ void C2_MacroAssembler::string_compare_long_same_encoding(Register result, Regis

// main loop
bind(NEXT_WORD);
// 8-byte aligned loads when AvoidUnalignedAccesses is enabled
// 8-byte aligned loads when UseUnalignedAccesses is not enabled
add(t0, str1, cnt2);
ld(tmp1, Address(t0));
add(t0, str2, cnt2);
Expand Down Expand Up @@ -1494,7 +1494,7 @@ void C2_MacroAssembler::arrays_equals(Register a1, Register a2,
la(a2, Address(a2, base_offset));

// Load 4 bytes once to compare for alignment before main loop.
if (AvoidUnalignedAccesses && (base_offset % 8) != 0) {
if (!UseUnalignedAccesses && (base_offset % 8) != 0) {
subi(cnt1, cnt1, elem_per_word / 2);
bltz(cnt1, TAIL03);
lwu(tmp1, Address(a1));
Expand All @@ -1509,7 +1509,7 @@ void C2_MacroAssembler::arrays_equals(Register a1, Register a2,
bltz(cnt1, SHORT);

#ifdef ASSERT
if (AvoidUnalignedAccesses) {
if (!UseUnalignedAccesses) {
Label align_ok;
orr(t0, a1, a2);
andi(t0, t0, 0x7);
Expand Down Expand Up @@ -1600,7 +1600,7 @@ void C2_MacroAssembler::string_equals(Register a1, Register a2,
mv(result, false);

// Load 4 bytes once to compare for alignment before main loop.
if (AvoidUnalignedAccesses && (base_offset % 8) != 0) {
if (!UseUnalignedAccesses && (base_offset % 8) != 0) {
subi(cnt1, cnt1, 4);
bltz(cnt1, TAIL03);
lwu(tmp1, Address(a1));
Expand All @@ -1615,7 +1615,7 @@ void C2_MacroAssembler::string_equals(Register a1, Register a2,
bltz(cnt1, SHORT);

#ifdef ASSERT
if (AvoidUnalignedAccesses) {
if (!UseUnalignedAccesses) {
Label align_ok;
orr(t0, a1, a2);
andi(t0, t0, 0x7);
Expand Down
6 changes: 3 additions & 3 deletions src/hotspot/cpu/riscv/macroAssembler_riscv.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -2894,7 +2894,7 @@ void MacroAssembler::load_short_misaligned(Register dst, Address src, Register t
if (granularity != 1 && granularity != 2) {
ShouldNotReachHere();
}
if (AvoidUnalignedAccesses && (granularity != 2)) {
if (!UseUnalignedAccesses && (granularity != 2)) {
assert_different_registers(dst, tmp);
assert_different_registers(tmp, src.base());
is_signed ? lb(tmp, Address(src.base(), src.offset() + 1)) : lbu(tmp, Address(src.base(), src.offset() + 1));
Expand All @@ -2908,7 +2908,7 @@ void MacroAssembler::load_short_misaligned(Register dst, Address src, Register t

// granularity is 1, 2 OR 4 bytes per load, if granularity 2 or 4 then dst and src.base() allowed to be the same register
void MacroAssembler::load_int_misaligned(Register dst, Address src, Register tmp, bool is_signed, int granularity) {
if (AvoidUnalignedAccesses && (granularity != 4)) {
if (!UseUnalignedAccesses && (granularity != 4)) {
switch(granularity) {
case 1:
assert_different_registers(dst, tmp, src.base());
Expand Down Expand Up @@ -2941,7 +2941,7 @@ void MacroAssembler::load_int_misaligned(Register dst, Address src, Register tmp

// granularity is 1, 2, 4 or 8 bytes per load, if granularity 4 or 8 then dst and src.base() allowed to be same register
void MacroAssembler::load_long_misaligned(Register dst, Address src, Register tmp, int granularity) {
if (AvoidUnalignedAccesses && (granularity != 8)) {
if (!UseUnalignedAccesses && (granularity != 8)) {
switch(granularity){
case 1:
assert_different_registers(dst, tmp, src.base());
Expand Down
6 changes: 3 additions & 3 deletions src/hotspot/cpu/riscv/stubGenerator_riscv.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -2617,7 +2617,7 @@ class StubGenerator: public StubCodeGenerator {
(UseCompressedClassPointers ? 8 : 4))) == 0, "Must be");

#ifdef ASSERT
if (AvoidUnalignedAccesses) {
if (!UseUnalignedAccesses) {
Label align_ok;
__ andi(t0, strL, 0x7);
__ beqz(t0, align_ok);
Expand Down Expand Up @@ -2679,7 +2679,7 @@ class StubGenerator: public StubCodeGenerator {
tmpU = isLU ? tmp2 : tmp1, // where to keep U for comparison
tmpL = isLU ? tmp1 : tmp2; // where to keep L for comparison

if (AvoidUnalignedAccesses && (base_offset % 8) != 0) {
if (!UseUnalignedAccesses && (base_offset % 8) != 0) {
// Load 4 bytes from strL to make sure main loop is 8-byte aligned
// cnt2 is >= 68 here, no need to check it for >= 0
__ lwu(tmpL, Address(strL));
Expand All @@ -2693,7 +2693,7 @@ class StubGenerator: public StubCodeGenerator {
__ subi(cnt2, cnt2, wordSize / 2);
}

// we are now 8-bytes aligned on strL when AvoidUnalignedAccesses is true
// we are now 8-bytes aligned on strL when UseUnalignedAccesses is false
__ subi(cnt2, cnt2, wordSize * 2);
__ bltz(cnt2, TAIL);
__ bind(SMALL_LOOP); // smaller loop
Expand Down
21 changes: 8 additions & 13 deletions src/hotspot/cpu/riscv/vm_version_riscv.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -158,12 +158,7 @@ void VM_Version::common_initialize() {
}
}

if (FLAG_IS_DEFAULT(AvoidUnalignedAccesses)) {
FLAG_SET_DEFAULT(AvoidUnalignedAccesses,
unaligned_scalar.value() != MISALIGNED_SCALAR_FAST);
}

if (!AvoidUnalignedAccesses) {
if (UseUnalignedAccesses) {
if (FLAG_IS_DEFAULT(UsePoly1305Intrinsics)) {
FLAG_SET_DEFAULT(UsePoly1305Intrinsics, true);
}
Expand Down Expand Up @@ -219,7 +214,7 @@ void VM_Version::common_initialize() {

// Misc Intrinsics that could depend on RVV.

if (!AvoidUnalignedAccesses && (UseZba || UseRVV)) {
if (UseUnalignedAccesses && (UseZba || UseRVV)) {
if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {
FLAG_SET_DEFAULT(UseCRC32Intrinsics, true);
}
Expand Down Expand Up @@ -309,7 +304,7 @@ void VM_Version::c2_initialize() {
FLAG_SET_DEFAULT(UseMulAddIntrinsic, true);
}

if (!AvoidUnalignedAccesses) {
if (UseUnalignedAccesses) {
if (FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) {
FLAG_SET_DEFAULT(UseMultiplyToLenIntrinsic, true);
}
Expand All @@ -318,7 +313,7 @@ void VM_Version::c2_initialize() {
FLAG_SET_DEFAULT(UseMultiplyToLenIntrinsic, false);
}

if (!AvoidUnalignedAccesses) {
if (UseUnalignedAccesses) {
if (FLAG_IS_DEFAULT(UseSquareToLenIntrinsic)) {
FLAG_SET_DEFAULT(UseSquareToLenIntrinsic, true);
}
Expand All @@ -327,7 +322,7 @@ void VM_Version::c2_initialize() {
FLAG_SET_DEFAULT(UseSquareToLenIntrinsic, false);
}

if (!AvoidUnalignedAccesses) {
if (UseUnalignedAccesses) {
if (FLAG_IS_DEFAULT(UseMontgomeryMultiplyIntrinsic)) {
FLAG_SET_DEFAULT(UseMontgomeryMultiplyIntrinsic, true);
}
Expand All @@ -336,7 +331,7 @@ void VM_Version::c2_initialize() {
FLAG_SET_DEFAULT(UseMontgomeryMultiplyIntrinsic, false);
}

if (!AvoidUnalignedAccesses) {
if (UseUnalignedAccesses) {
if (FLAG_IS_DEFAULT(UseMontgomerySquareIntrinsic)) {
FLAG_SET_DEFAULT(UseMontgomerySquareIntrinsic, true);
}
Expand Down Expand Up @@ -371,7 +366,7 @@ void VM_Version::c2_initialize() {
FLAG_SET_DEFAULT(UseChaCha20Intrinsics, false);
}

if (!AvoidUnalignedAccesses) {
if (UseUnalignedAccesses) {
if (FLAG_IS_DEFAULT(UseMD5Intrinsics)) {
FLAG_SET_DEFAULT(UseMD5Intrinsics, true);
}
Expand All @@ -386,7 +381,7 @@ void VM_Version::c2_initialize() {
}

// SHA-1, no RVV required though.
if (UseSHA && !AvoidUnalignedAccesses) {
if (UseSHA && UseUnalignedAccesses) {
if (FLAG_IS_DEFAULT(UseSHA1Intrinsics)) {
FLAG_SET_DEFAULT(UseSHA1Intrinsics, true);
}
Expand Down