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Remove debug parameter output
The bus interface used to output the interface type at start of simulation. This was maybe useful for debugging but can be deprecated.
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rtl/verilog/mor1kx_bus_if_wb32.v

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@@ -53,9 +53,6 @@ module mor1kx_bus_if_wb32
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(BURST_LENGTH==8) ? 3 :
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(BURST_LENGTH==16)? 4 : 30;
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initial
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$display("%m: Wishbone bus IF is %s",BUS_IF_TYPE);
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generate
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/* verilator lint_off WIDTH */
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if (BUS_IF_TYPE=="B3_READ_BURSTING") begin : b3_read_bursting

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