Interrupt Controller

A project to implement and test interrupt controller using Questasim software.

Design and Testbench made using Verilog.
Supports programming priorities for each device using Advanced Peripheral Bus(APB) protocol by master.
Developed testbench with various test cases to verify controller working when programmed for different priorities.

Files

Name		Name	Last commit message	Last commit date
Latest commit History 19 Commits
System Verilog		System Verilog
Verilog		Verilog
README.md		README.md

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