Mersenne-Twister-HLS

High Level Synthesis implementation of the popular Mersenne Twister pseudo-random number generator. Sources and project settings to build a VHDL or Verilog module that will provide a pseudorandom number generation. The module will generate a stream of 32 bit psuedo-randoms at 500 MHz (according to the HLS report) on Virtex 7 FPGA using very modest resources. Project should be very easy to adapt to more recent Xilinx FPGA's and possibly to older FPGA's as well. I've done this project mostly as a self learning exercise - but if you find it useful in real hardware - that's great! Let me know if you have any questions and definitely shoot me a line if you do end up using it or adopting it.

How to build and verify the functionality

1. Clone/fork the repository using the command hints above on this page
2. Start vivado_hls
3. Open Project --> navigate inside the project you just checked out and highlight mtwist_prj --> Click 'OK'
4. 'Explorer' pane should be visible on the left. Highlight 'HLS Solution'
5. Build the RTL model by clicking on 'Run Synthesis' button
6. Synthesis(HLS_Solution) pane should appear in the center panel telling you that the design should be able to run with 2ns clock and consume 16 BRAMs, 4 DSPs and ~2.5k FFs and LUTs
7. Now verify the design by clicking 'Run C/RTL Cosimulation' This will compare 20k pseudorandom numbers generated by the RTL and by a C testbench. The data for comparison have een pre-generated and saved in rand.dat. If everything works a new pane in the center panel titled 'Simulation(HLS_Solution)' should appear telling you that Status is 'Pass'
8. You should be now able to Export the design into your project using 'Solution'-->'Export RTL' and selecting the options appropriate for your use case.