Indirect call reduction for Jit code #9579
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ext/opcache/jit/zend_jit_x86.dasc
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| @@ -150,6 +150,9 @@ static size_t tsrm_tls_offset; | |||
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| #define IS_32BIT(addr) (((uintptr_t)(addr)) <= 0x7fffffff) | |||
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| /* Call range is before or after 2GB */ | |||
| #define IS_NEAR(end_addr, func) ((((uintptr_t)(end_addr)^(uintptr_t)(func)) >> 33) == 0) | |||
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I didn't understand this condition. Why shift to 33 bits?
I think it also should take care about dasm_buf
I would propose:
#define MAY_USE_32BIT_ADDR(addr) \
(IS_SIGNED_32BIT((char*)(addr) - (char*)dasm_buf) && \
IS_SIGNED_32BIT((char*)(addr) - (char*)dasm_end))
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@dstogov Thanks for the proposal and we will use it. And we did make a big mistake here for right shifting 33 bits and we actually should right shift 31 bits, because what we are trying to check is that the highest 33 bits must all be zeros after XOR operation.
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@dstogov Thanks for your proposal. How about this implementation? Bit operation is a little bit faster ( about 10 TPS in our workload ), though with less code readability.
#define IS_NEAR(end_addr, func) ((((uintptr_t)(end_addr)^(uintptr_t)(func)) >> 31) == 0)
|| if (IS_NEAR(dasm_buf, func) && IS_NEAR(dasm_end, func)) {
| call qword &func
|| }
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Your implementation guarantees that the top 33 bits are the same, but this check is not accurate enough.
0x80000000 - 0x7fff0000 = 0x10000 (valid 32-bit offset)
(0x80000000 ^ 0x7fff0000) >> 31 = 1 (your implementation thinks it's invalid)
It's possible to create a faster check, but this is not very critical operation.
I wouldn't use name "NEAR" to avoid mess with far/near addresses in 16-bit x86 terminology.
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My fault and thanks a lot. I updated it.
Changing indirect call to direct call for Jit code benefits the branch prediction, which gets 1% performance gain in our workload. Similarly, we change indirect jump to direct jump. Signed-off-by: Su, Tao <tao.su@intel.com> Signed-off-by: Wang, Xue <xue1.wang@intel.com>
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Merged as 52f4ed16. Thank you ! |
Changing indirect call to direct call for Jit code benefits the branch prediction, which gets 1% performance gain in our workload.
Similarly, we change indirect jump to direct jump.
Signed-off-by: Su, Tao tao.su@intel.com
Signed-off-by: Wang, Xue xue1.wang@intel.com