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riscv: thead: Add support for XTheadMac ISA extension
The XTheadMac ISA extension provides multiply-accumulate/subtract instructions: * mula/mulaw/mulah * muls/mulsw/mulsh To benefit from middle-end passes, we expand the following named patterns in riscv.md (as they are not T-Head-specific): * maddhisi4 * msubhisi4 gcc/ChangeLog: * config/riscv/riscv.md (maddhisi4): New expand. (msubhisi4): New expand. * config/riscv/thead.md (*th_mula<mode>): New pattern. (*th_mulawsi): New pattern. (*th_mulawsi2): New pattern. (*th_maddhisi4): New pattern. (*th_sextw_maddhisi4): New pattern. (*th_muls<mode>): New pattern. (*th_mulswsi): New pattern. (*th_mulswsi2): New pattern. (*th_msubhisi4): New pattern. (*th_sextw_msubhisi4): New pattern. gcc/testsuite/ChangeLog: * gcc.target/riscv/thead-mula-muls.c: New test. Co-Developed-by: Xianmiao Qu <cooper.qu@linux.alibaba.com> Signed-off-by: Xianmiao Qu <cooper.qu@linux.alibaba.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu> Changed in v2: - Add missing prefix in on INSN
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,43 @@ | ||
| /* { dg-do compile } */ | ||
| /* { dg-options "-march=rv32gc_xtheadmac" { target { rv32 } } } */ | ||
| /* { dg-options "-march=rv64gc_xtheadmac" { target { rv64 } } } */ | ||
| /* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Og" } } */ | ||
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| long f_mula(long a, long b, long c) | ||
| { | ||
| return a + b * c; | ||
| } | ||
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| long f_muls(long a, long b, long c) | ||
| { | ||
| return a - b * c; | ||
| } | ||
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| #if __riscv_xlen == 64 | ||
| int f_mulaw(int a, int b, int c) | ||
| { | ||
| return a + b * c; | ||
| } | ||
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| int f_mulsw(int a, int b, int c) | ||
| { | ||
| return a - b * c; | ||
| } | ||
| #endif | ||
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| long f_mulah(int a, unsigned short b, unsigned short c) | ||
| { | ||
| return a + (int)(short)b * (int)(short)c; | ||
| } | ||
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| long f_mulsh(int a, unsigned short b, unsigned short c) | ||
| { | ||
| return a - (int)(short)b * (int)(short)c; | ||
| } | ||
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| /* { dg-final { scan-assembler-times "th.mula\t" 1 } } */ | ||
| /* { dg-final { scan-assembler-times "th.muls\t" 1 } } */ | ||
| /* { dg-final { scan-assembler-times "th.mulaw\t" 1 { target { rv64 } } } } */ | ||
| /* { dg-final { scan-assembler-times "th.mulsw\t" 1 { target { rv64 } } } } */ | ||
| /* { dg-final { scan-assembler-times "th.mulah\t" 1 } } */ | ||
| /* { dg-final { scan-assembler-times "th.mulsh\t" 1 } } */ |