Skip to content

Commit a646fcf

Browse files
ZideChen0wenlingz
authored andcommitted
hv: fix 'No brackets to then/else' in vpci code
This patch addes missing brackets for 'if/else' statements based on MISRA-C requirements 12 S. Tracked-On: #861 Signed-off-by: Zide Chen <zide.chen@intel.com> Acked-by: Anthony Xu <anthony.xu@intel.com> Reviewed-by: Huihuang Shi <huihuang.shi@intel.com>
1 parent bad813e commit a646fcf

File tree

1 file changed

+23
-19
lines changed

1 file changed

+23
-19
lines changed

hypervisor/dm/vpci/vpci.c

Lines changed: 23 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -64,19 +64,21 @@ static uint32_t pci_cfg_io_read(struct acrn_vm *vm, uint16_t addr, size_t bytes)
6464
val |= PCI_CFG_ENABLE;
6565
}
6666
}
67-
} else if (is_cfg_data(addr)) {
68-
if (pi->cached_enable) {
69-
uint16_t offset = addr - PCI_CONFIG_DATA;
67+
} else {
68+
if (is_cfg_data(addr)) {
69+
if (pi->cached_enable) {
70+
uint16_t offset = addr - PCI_CONFIG_DATA;
7071

71-
if ((vpci->ops != NULL) && (vpci->ops->cfgread != NULL)) {
72-
vpci->ops->cfgread(vpci, pi->cached_bdf,
73-
pi->cached_reg + offset, bytes, &val);
74-
}
72+
if ((vpci->ops != NULL) && (vpci->ops->cfgread != NULL)) {
73+
vpci->ops->cfgread(vpci, pi->cached_bdf,
74+
pi->cached_reg + offset, bytes, &val);
75+
}
7576

76-
pci_cfg_clear_cache(pi);
77+
pci_cfg_clear_cache(pi);
78+
}
79+
} else {
80+
val = 0xFFFFFFFFU;
7781
}
78-
} else {
79-
val = 0xFFFFFFFFU;
8082
}
8183

8284
return val;
@@ -95,18 +97,20 @@ static void pci_cfg_io_write(struct acrn_vm *vm, uint16_t addr, size_t bytes,
9597
pi->cached_reg = val & PCI_REGMAX;
9698
pi->cached_enable = ((val & PCI_CFG_ENABLE) == PCI_CFG_ENABLE);
9799
}
98-
} else if (is_cfg_data(addr)) {
99-
if (pi->cached_enable) {
100-
uint16_t offset = addr - PCI_CONFIG_DATA;
100+
} else {
101+
if (is_cfg_data(addr)) {
102+
if (pi->cached_enable) {
103+
uint16_t offset = addr - PCI_CONFIG_DATA;
101104

102-
if ((vpci->ops != NULL) && (vpci->ops->cfgwrite != NULL)) {
103-
vpci->ops->cfgwrite(vpci, pi->cached_bdf,
104-
pi->cached_reg + offset, bytes, val);
105+
if ((vpci->ops != NULL) && (vpci->ops->cfgwrite != NULL)) {
106+
vpci->ops->cfgwrite(vpci, pi->cached_bdf,
107+
pi->cached_reg + offset, bytes, val);
108+
}
109+
pci_cfg_clear_cache(pi);
105110
}
106-
pci_cfg_clear_cache(pi);
111+
} else {
112+
pr_err("Not PCI cfg data/addr port access!");
107113
}
108-
} else {
109-
pr_err("Not PCI cfg data/addr port access!");
110114
}
111115
}
112116

0 commit comments

Comments
 (0)