Astral new #110
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Astral new #110
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* target/sim: Add JTAG tasks to read/write 32b registers * target/sim: Add JTAG task to halt and load binary Can be used by platforms to halt CVA6 and preload a shared memory when execution happens on domains different than Cheshire. * target/sim: Clean up added tasks --------- Co-authored-by: Paul Scheffler <paulsc@iis.ee.ethz.ch>
* hw: Add `RegAdaptMemCut` inside `axi_to_reg_v2` * Bender.yml: Update `register_interface` * target/xilinx: Clean up flow, multi-board support, add VCU128 * sw: Update CVA6 SDK, add multi-device-tree flow * doc: Add new Xilinx target features * target/xilinx: Make utility targets weekly depend on input files * util: Add HS2 OpenOCD script, amend docs * doc: Some cleanup * nonfree: Update * doc: Fix typo --------- Co-authored-by: Cyril Koenig <cykoenig@iis.ee.ethz.ch>
added 5 commits
April 19, 2024 18:39
Aquaticfuller
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Jul 16, 2024
carfield.mk: Increase serial link data lanes to 8
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