We read every piece of feedback, and take your input very seriously.
To see all available qualifiers, see our documentation.
16QAM modulation and demodulation by Verilog
There was an error while loading. Please reload this page.
使用FPGA完成16QAM的调制解调
设置FIR的IP核的时候不小心存错地方了,懒得改了
other里面是matlab进行正余弦采样和滤波器设计的代码
报告