Skip to content
View rayhan-shhadeh's full-sized avatar
🎯
Focusing
🎯
Focusing

Organizations

@Raia-Ishtayeh

Block or report rayhan-shhadeh

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
rayhan-shhadeh/README.md

Hi there 👋

I'm a passionate Computer Engineering student with a strong foundation in software and hardware design. Here's a bit about me:

  • 🔭 I’m currently working on projects involving C, C++, Verilog, VHDL, Java, and JavaScript.
  • 🌱 I’m constantly learning and expanding my skills in both software development and Hardware.
  • 👯 I’m looking to collaborate on exciting projects that push the boundaries of technology.
  • 💬 Ask me about my projects, coursework, or anything tech-related!

Get in Touch

Fun Facts

  • 🚀 I love exploring new technologies and applying them to solve real-world problems.
  • 🎮 In my free time, you can find me gaming or working on personal coding projects.
  • 🌎 I enjoy connecting with people from around the world and learning about different cultures and technologies.

My Skills

C C++ Java JavaScript Verilog Static Badge Static Badge postman Static Badge

GitHub Stats

Your GitHub Stats Top Langs

Pinned Loading

  1. ai-hw1-grid-solver ai-hw1-grid-solver Public

    JavaScript 1

  2. mutlicalss-classification-AI-HW2 mutlicalss-classification-AI-HW2 Public

    Python

  3. networks1_HW2_p1_tcp networks1_HW2_p1_tcp Public

    Java

  4. DimaNEid/CommunityCraftAdvancedSoft DimaNEid/CommunityCraftAdvancedSoft Public

    JavaScript

  5. rayhanshhadeh.github.io rayhanshhadeh.github.io Public

    HTML

  6. VLSI-Design-Verification VLSI-Design-Verification Public

    This repository is dedicated to my VLSI Design Verification Course Exercises and Projects

    SystemVerilog