Support Metrics DSim sumulator

[taichi-ishitani]

https://www.metrics.ca/product

[taichi-ishitani]

Clash is reported during elaborating VHDL TB.

=F:[Crash] 
This Metrics software product has crashed due to an internal error.
Please seek assistance from Metrics support personnel.
Additional information may follow.

Item being generated at the time of the crash:
    (0x7fa2c76ca230:VHDL value::VHDL array constant[AD]) @ /home/taichi/workspace/etc/rggen-sample-testbench/rtl/rggen-vhdl-rtl/rggen_adapter_common.vhd:53 during generation of right side value

https://github.com/rggen/rggen-vhdl-rtl/blob/219fdd5a1d38f043b8e42fca3ee14e9ba905f1cf/rggen_adapter_common.vhd#L53

To prevent this error, the resize function needs to be replaced like below.

  function get_begin_address (
    base_addess:  unsigned
  ) return unsigned is
    alias     base:           unsigned(base_addess'length - 1 downto 0) is base_addess;
    variable  begin_address:  unsigned(ADDRESS_WIDTH - 1 downto 0);
  begin
    for i in 0 to ADDRESS_WIDTH - 1 loop
      if i < BASE_ADDRESS'length then
        begin_address(i)  := base(i);
      else
        begin_address(i)  := '0';
      end if;
    end loop;

    return begin_address;
  end get_begin_address;

  constant  BEGIN_ADDRESS:  unsigned(ADDRESS_WIDTH - 1 downto 0)  := get_begin_address(BASE_ADDRESS);
  constant  END_ADDRESS:    unsigned(ADDRESS_WIDTH - 1 downto 0)  := BEGIN_ADDRESS + BYTE_SIZE - 1;

[taichi-ishitani]

A null handle access error occurs during executing ral_access_test on the VHDL TB.

=W:[Assoc] accessing 'vif' @ /home/taichi/workspace/etc/rggen-sample-testbench/rtl/rggen-sv-rtl/rggen_backdoor_pkg.sv:20: key not found in array.
=F:[NullRef] null handle 'vif' dereferenced @ /home/taichi/workspace/etc/rggen-sample-testbench/ral/rggen-sv-ral/rggen_ral_backdoor_pkg.sv:56
=T:Simulation terminated due to null handle dereference.
=N:Backtrace:
# 1: dsim_null_handle
# 2: task rggen_ral_backdoor_pkg::rggen_backdoor::read
# 3: task rggen_ral_pkg::rggen_ral_reg::backdoor_read
# 4: task uvm_pkg::uvm_reg::do_read
# 5: task rggen_ral_pkg::rggen_ral_reg::do_read
# 6: task uvm_pkg::uvm_reg::XreadX
# 7: task uvm_pkg::uvm_reg::mirror
# 8: task tue_pkg::tue_reg_single_access_seq::verify_access
# 9: task tue_pkg::tue_reg_single_access_seq::body
#10: fork thread uvm_pkg::uvm_sequence_base::start
#11: task uvm_pkg::uvm_sequence_base::start
#12: task uvm_pkg::uvm_reg_access_seq::do_block
#13: task tue_pkg::tue_reg_access_seq::body
#14: fork thread uvm_pkg::uvm_sequence_base::start
#15: task uvm_pkg::uvm_sequence_base::start
#16: task env_pkg::ral_test_sequence#(class tue_pkg::tue_reg_access_seq)::body
#17: fork thread uvm_pkg::uvm_sequence_base::start
#18: task uvm_pkg::uvm_sequence_base::start
#19: fork thread uvm_pkg::uvm_sequencer_base::start_phase_sequence
#20: function uvm_pkg::uvm_sequencer_base::start_phase_sequence
#21: function tue_pkg::tue_sequencer_base#(class uvm_pkg::uvm_sequencer#(class uvm_pkg::uvm_sequence_item,class uvm_pkg::uvm_sequence_item),class env_pkg::env_configuration,class tue_pkg::tue_status_dummy,class env_pkg::env_configuration,class tue_pkg::tue_status_dummy)::start_phase_sequence
#22: task uvm_pkg::uvm_phase::execute_phase
#23: fork thread uvm_pkg::uvm_phase::m_run_phases
#24: begin-end uvm_pkg::uvm_phase::m_run_phases
#25: task uvm_pkg::uvm_phase::m_run_phases
#26: fork thread uvm_pkg::uvm_root::run_test
#27: task uvm_pkg::uvm_root::run_test
#28: task uvm_pkg::run_test
#29: task top.run_ral_test
#30: initial block top

It caused this error that dsim uses () for element selection of generat for loop instead of [].

top.u_block_0.g_register_11.g(0).g(0).u_register.u_register_common.u_backdoor

To fix this error, () should be replaced with [].

[taichi-ishitani]

=E:[TypeMismatchXlang]:
    The following cross-language type conversions are not supported:    

    /home/taichi/workspace/etc/rggen-sample-testbench/env/axi4lite_top.sv:182:46    boolean             
                                                                                    bit signed[31:0]    

    /home/taichi/workspace/etc/rggen-sample-testbench/env/axi4lite_top.sv:183:46    boolean             
                                                                                    bit signed[31:0]   

To fix this error, need to specify width expressly.

[taichi-ishitani]

Clash is reported during elaborating VHDL TB.

=F:[Crash] 
This Metrics software product has crashed due to an internal error.
Please seek assistance from Metrics support personnel.
Additional information may follow.

Item being generated at the time of the crash:
    (0x7fa2c76ca230:VHDL value::VHDL array constant[AD]) @ /home/taichi/workspace/etc/rggen-sample-testbench/rtl/rggen-vhdl-rtl/rggen_adapter_common.vhd:53 during generation of right side value

https://github.com/rggen/rggen-vhdl-rtl/blob/219fdd5a1d38f043b8e42fca3ee14e9ba905f1cf/rggen_adapter_common.vhd#L53

To prevent this error, the resize function needs to be replaced like below.

  function get_begin_address (
    base_addess:  unsigned
  ) return unsigned is
    alias     base:           unsigned(base_addess'length - 1 downto 0) is base_addess;
    variable  begin_address:  unsigned(ADDRESS_WIDTH - 1 downto 0);
  begin
    for i in 0 to ADDRESS_WIDTH - 1 loop
      if i < BASE_ADDRESS'length then
        begin_address(i)  := base(i);
      else
        begin_address(i)  := '0';
      end if;
    end loop;

    return begin_address;
  end get_begin_address;

  constant  BEGIN_ADDRESS:  unsigned(ADDRESS_WIDTH - 1 downto 0)  := get_begin_address(BASE_ADDRESS);
  constant  END_ADDRESS:    unsigned(ADDRESS_WIDTH - 1 downto 0)  := BEGIN_ADDRESS + BYTE_SIZE - 1;

The BASE_ADDRESS parameter is unsized.

rggen-sample-testbench/rtl/apb/block_0.vhd

Line 11 in c1a5785

BASE_ADDRESS: unsigned := x"0";

It seems that this parameter is not set correctly from SV TB.

rggen-sample-testbench/env/apb_top.sv

Line 187 in c1a5785

.BASE_ADDRESS ("0001000000000000" ),

In fact, if this line is removed then no cash error is happened and simulation works fine.

[taichi-ishitani]

DSIM is a pre-define macro showing dsim is used.

[taichi-ishitani]

Clash is reported during elaborating VHDL TB.

=F:[Crash] 
This Metrics software product has crashed due to an internal error.
Please seek assistance from Metrics support personnel.
Additional information may follow.

Item being generated at the time of the crash:
    (0x7fa2c76ca230:VHDL value::VHDL array constant[AD]) @ /home/taichi/workspace/etc/rggen-sample-testbench/rtl/rggen-vhdl-rtl/rggen_adapter_common.vhd:53 during generation of right side value

https://github.com/rggen/rggen-vhdl-rtl/blob/219fdd5a1d38f043b8e42fca3ee14e9ba905f1cf/rggen_adapter_common.vhd#L53
To prevent this error, the resize function needs to be replaced like below.

  function get_begin_address (
    base_addess:  unsigned
  ) return unsigned is
    alias     base:           unsigned(base_addess'length - 1 downto 0) is base_addess;
    variable  begin_address:  unsigned(ADDRESS_WIDTH - 1 downto 0);
  begin
    for i in 0 to ADDRESS_WIDTH - 1 loop
      if i < BASE_ADDRESS'length then
        begin_address(i)  := base(i);
      else
        begin_address(i)  := '0';
      end if;
    end loop;

    return begin_address;
  end get_begin_address;

  constant  BEGIN_ADDRESS:  unsigned(ADDRESS_WIDTH - 1 downto 0)  := get_begin_address(BASE_ADDRESS);
  constant  END_ADDRESS:    unsigned(ADDRESS_WIDTH - 1 downto 0)  := BEGIN_ADDRESS + BYTE_SIZE - 1;

The BASE_ADDRESS parameter is unsized.

rggen-sample-testbench/rtl/apb/block_0.vhd

Line 11 in c1a5785

BASE_ADDRESS: unsigned := x"0";

It seems that this parameter is not set correctly from SV TB.

rggen-sample-testbench/env/apb_top.sv

Line 187 in c1a5785

.BASE_ADDRESS ("0001000000000000" ),

In fact, if this line is removed then no cash error is happened and simulation works fine.

I put the sample code to reproduce this error.
https://gist.github.com/taichi-ishitani/97927543fa14edd95a84bd7f9be04115

[taichi-ishitani]

Clash is reported during elaborating VHDL TB.

=F:[Crash] 
This Metrics software product has crashed due to an internal error.
Please seek assistance from Metrics support personnel.
Additional information may follow.

Item being generated at the time of the crash:
    (0x7fa2c76ca230:VHDL value::VHDL array constant[AD]) @ /home/taichi/workspace/etc/rggen-sample-testbench/rtl/rggen-vhdl-rtl/rggen_adapter_common.vhd:53 during generation of right side value

https://github.com/rggen/rggen-vhdl-rtl/blob/219fdd5a1d38f043b8e42fca3ee14e9ba905f1cf/rggen_adapter_common.vhd#L53
To prevent this error, the resize function needs to be replaced like below.

  function get_begin_address (
    base_addess:  unsigned
  ) return unsigned is
    alias     base:           unsigned(base_addess'length - 1 downto 0) is base_addess;
    variable  begin_address:  unsigned(ADDRESS_WIDTH - 1 downto 0);
  begin
    for i in 0 to ADDRESS_WIDTH - 1 loop
      if i < BASE_ADDRESS'length then
        begin_address(i)  := base(i);
      else
        begin_address(i)  := '0';
      end if;
    end loop;

    return begin_address;
  end get_begin_address;

  constant  BEGIN_ADDRESS:  unsigned(ADDRESS_WIDTH - 1 downto 0)  := get_begin_address(BASE_ADDRESS);
  constant  END_ADDRESS:    unsigned(ADDRESS_WIDTH - 1 downto 0)  := BEGIN_ADDRESS + BYTE_SIZE - 1;

The BASE_ADDRESS parameter is unsized.

rggen-sample-testbench/rtl/apb/block_0.vhd

Line 11 in c1a5785

BASE_ADDRESS: unsigned := x"0";

It seems that this parameter is not set correctly from SV TB.

rggen-sample-testbench/env/apb_top.sv

Line 187 in c1a5785

.BASE_ADDRESS ("0001000000000000" ),

In fact, if this line is removed then no cash error is happened and simulation works fine.

I put the sample code to reproduce this error. https://gist.github.com/taichi-ishitani/97927543fa14edd95a84bd7f9be04115

This DSim bug was fixed.
https://help.metrics.ca/support/discussions/topics/154000634959