Update RVV v1.0 (until the vlmul change) based on the binutils-2.35 #224
Conversation
2020-05-16 Jim Wilson <jimw@sifive.com> Kito Cheng <kito.cheng@sifive.com> Nelson Chu <nelson.chu@sifive.com>
These instruction are added back in the risc-v vector spec, commit 0fec0e257cca5e389a0e1774e7d5aaac729b4ad2, Added clarifications on loads/stores. Note that the base V extension only enable the single register load/store variant with <nf> is 0. It is clear to me that how to enable other register load/store is <nf> is 2, 4, 8, so I will add the limitation when it is clarified.
These instruction are removed in the risc-v vector spec, commit 0fec0e257cca5e389a0e1774e7d5aaac729b4ad2, Added clarifications on loads/stores.
An integer value can be halved in width using the narrowing integer shift instructions with a scalar operand of x0. Can define assembly pseudo instruction "vncvt.x.x.v vd,vs,vm" to "vnsrl.wx vd,vs,x0,vm".
Add new instruction vfrsqrte7.v and vfrece7.v. The former set VFUNARY1 (vs1) to 00100, and the later set VFUNARY1 to 00101.
Add load instructions which have an EEW encoded in the `mew` and `width`.
Remove the V-ext v0.7 in the riscv_ext_version_table, and regard V-ext as a non-ISA spec extension temporarily. Since we only support the v1.0 for now, and not yet upstreamed. Also, we define other unratified extensions to the non-ISA spec extension, too.
|
This looks OK to me. I think we missed a problem with dest/mask register overlaps when the mask length changed to 1 bit per element. The v0.8 spec says "The destination vector register group for a masked vector instruction can only overlap the source mask register (v0) when LMUL=1. Otherwise, an illegal instruction exception is raised." Since we can't know LMUL we don't check this in the assembler. However, in v1.0 is says "NOTE: Some masked instructions that target There seems to be a problem with how zvamo and zvlsseg are handled. The current text says "This instruction subset is given the ISA string I think these issues can be fixed with follow on patches, if necessary. |
|
@aswaterman do you mind disambiguate for this?
@aswaterman Does it what you mean? my understanding is V = zvbase + zvamo + zvlsseg no matter the target triple. |
|
@kito-cheng that's my understanding, too. The problem is that no one ever formally defined the name Zvbase, so there's no way to refer to that piece; you should raise that issue on the vector spec. |
Thanks for the reminder, I will start to handle this next week. |
|
I will start to update the mask overlap issue this week. As for the Zvbase, we will create an issue on the vector spec to discuss it. Thanks for all @jim-wilson @aswaterman @kito-cheng |
|
Need sub-extension for baseline vector ISA: riscvarchive/riscv-v-spec#546 |
There are nine commits here,
RISC-V: Support RVV according to vector spec v1.0-draft-20200516.
This commit is ported from rvv-0.9.x branch. Basically, this is the v0.9 implementation.
Extend the VLR and VSR instruction, when is 2, 4, 8.
Remove Vector indexed instruction when EEW >= 128.
riscvarchive/riscv-v-spec@0fec0e2#diff-4fa320b4e415eee7270590bb06607389R1923
Add assembly pseudo instructions vncvt.x.x.v.
riscvarchive/riscv-v-spec@2ab0b81
Added reciprocal and reciprocal square-root estimate instruction.
riscvarchive/riscv-v-spec@d35b23f
Added element width hint to whole register loads/stores.
riscvarchive/riscv-v-spec@20f673c
Added vrgatherei16 instruction.
riscvarchive/riscv-v-spec@a679250
Make vlmul bits contiguous in vtype.
riscvarchive/riscv-v-spec@b8cd98b
RISC-V: Clarify the supported versions for the unratified extensions.
Based on the recent changes in the binutils-2.35 (-misa-spec option), we probably need to set the draft versions for those UN-ratified extensions. This commit will set the current v1.0 to the V and it's sub extensions correctly by default. Note that only one default draft version can be accepted for an extension, since there is no ISA spec define them. If the next draft is released, then we must remember to update the draft version in the riscv_ext_version_table.