Add #[rustc_legacy_const_generics] to all intrinsics with const-generic parameters

crates/core_arch/src/loongarch32/mod.rs

@@ -16,6 +16,7 @@ unsafe extern "unadjusted" {
 
 /// Generates the cache operation instruction
 #[inline]
+#[rustc_legacy_const_generics(0, 2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub unsafe fn cacop<const IMM5: i32, const IMM_S12: i32>(b: i32) {
     static_assert_uimm_bits!(IMM5, 5);
@@ -25,6 +26,7 @@ pub unsafe fn cacop<const IMM5: i32, const IMM_S12: i32>(b: i32) {
 
 /// Reads the CSR
 #[inline]
+#[rustc_legacy_const_generics(0)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub unsafe fn csrrd<const IMM14: i32>() -> i32 {
     static_assert_uimm_bits!(IMM14, 14);
@@ -33,6 +35,7 @@ pub unsafe fn csrrd<const IMM14: i32>() -> i32 {
 
 /// Writes the CSR
 #[inline]
+#[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub unsafe fn csrwr<const IMM14: i32>(a: i32) -> i32 {
     static_assert_uimm_bits!(IMM14, 14);
@@ -41,6 +44,7 @@ pub unsafe fn csrwr<const IMM14: i32>(a: i32) -> i32 {
 
 /// Exchanges the CSR
 #[inline]
+#[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub unsafe fn csrxchg<const IMM14: i32>(a: i32, b: i32) -> i32 {
     static_assert_uimm_bits!(IMM14, 14);

crates/core_arch/src/loongarch64/mod.rs

@@ -63,6 +63,7 @@ pub fn crcc_w_d_w(a: i64, b: i32) -> i32 {
 
 /// Generates the cache operation instruction
 #[inline]
+#[rustc_legacy_const_generics(0, 2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub unsafe fn cacop<const IMM5: i64, const IMM_S12: i64>(b: i64) {
     static_assert_uimm_bits!(IMM5, 5);
@@ -72,6 +73,7 @@ pub unsafe fn cacop<const IMM5: i64, const IMM_S12: i64>(b: i64) {
 
 /// Reads the CSR
 #[inline]
+#[rustc_legacy_const_generics(0)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub unsafe fn csrrd<const IMM14: i32>() -> i64 {
     static_assert_uimm_bits!(IMM14, 14);
@@ -80,6 +82,7 @@ pub unsafe fn csrrd<const IMM14: i32>() -> i64 {
 
 /// Writes the CSR
 #[inline]
+#[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub unsafe fn csrwr<const IMM14: i32>(a: i64) -> i64 {
     static_assert_uimm_bits!(IMM14, 14);
@@ -88,6 +91,7 @@ pub unsafe fn csrwr<const IMM14: i32>(a: i64) -> i64 {
 
 /// Exchanges the CSR
 #[inline]
+#[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub unsafe fn csrxchg<const IMM14: i32>(a: i64, b: i64) -> i64 {
     static_assert_uimm_bits!(IMM14, 14);

crates/core_arch/src/loongarch_shared/mod.rs

@@ -114,6 +114,7 @@ pub fn crcc_w_w_w(a: i32, b: i32) -> i32 {
 
 /// Generates the memory barrier instruction
 #[inline]
+#[rustc_legacy_const_generics(0)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn dbar<const IMM15: i32>() {
     static_assert_uimm_bits!(IMM15, 15);
@@ -122,6 +123,7 @@ pub fn dbar<const IMM15: i32>() {
 
 /// Generates the instruction-fetch barrier instruction
 #[inline]
+#[rustc_legacy_const_generics(0)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn ibar<const IMM15: i32>() {
     static_assert_uimm_bits!(IMM15, 15);
@@ -130,6 +132,7 @@ pub fn ibar<const IMM15: i32>() {
 
 /// Moves data from a GPR to the FCSR
 #[inline]
+#[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub unsafe fn movgr2fcsr<const IMM2: i32>(a: i32) {
     static_assert_uimm_bits!(IMM2, 2);
@@ -138,6 +141,7 @@ pub unsafe fn movgr2fcsr<const IMM2: i32>(a: i32) {
 
 /// Moves data from a FCSR to the GPR
 #[inline]
+#[rustc_legacy_const_generics(0)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub fn movfcsr2gr<const IMM2: i32>() -> i32 {
     static_assert_uimm_bits!(IMM2, 2);
@@ -188,6 +192,7 @@ pub unsafe fn iocsrwr_w(a: i32, b: i32) {
 
 /// Generates the breakpoint instruction
 #[inline]
+#[rustc_legacy_const_generics(0)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub unsafe fn brk<const IMM15: i32>() {
     static_assert_uimm_bits!(IMM15, 15);
@@ -203,6 +208,7 @@ pub fn cpucfg(a: i32) -> i32 {
 
 /// Generates the syscall instruction
 #[inline]
+#[rustc_legacy_const_generics(0)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
 pub unsafe fn syscall<const IMM15: i32>() {
     static_assert_uimm_bits!(IMM15, 15);

crates/core_arch/src/powerpc/altivec.rs

@@ -4073,6 +4073,7 @@ where
 /// Vector Convert to Signed Integer
 #[inline]
 #[target_feature(enable = "altivec")]
+#[rustc_legacy_const_generics(1)]
 #[cfg_attr(test, assert_instr(vctsxs, IMM5 = 1))]
 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
 pub unsafe fn vec_cts<const IMM5: i32>(a: vector_float) -> vector_signed_int {
@@ -4084,6 +4085,7 @@ pub unsafe fn vec_cts<const IMM5: i32>(a: vector_float) -> vector_signed_int {
 /// Vector Convert to Unsigned Integer
 #[inline]
 #[target_feature(enable = "altivec")]
+#[rustc_legacy_const_generics(1)]
 #[cfg_attr(test, assert_instr(vctuxs, IMM5 = 1))]
 #[unstable(feature = "stdarch_powerpc", issue = "111145")]
 pub unsafe fn vec_ctu<const IMM5: i32>(a: vector_float) -> vector_unsigned_int {

crates/core_arch/src/s390x/vector.rs

@@ -4558,6 +4558,7 @@ pub unsafe fn vec_unpackl<T: sealed::VectorUnpackl>(a: T) -> <T as sealed::Vecto
 /// in the corresponding byte element of d are set to ones. Otherwise, if the bit is zero, the corresponding byte element is set to zero.
 #[inline]
 #[target_feature(enable = "vector")]
+#[rustc_legacy_const_generics(0)]
 #[unstable(feature = "stdarch_s390x", issue = "135681")]
 #[cfg_attr(test, assert_instr(vgbm, MASK = 0x00FF))]
 pub unsafe fn vec_genmask<const MASK: u16>() -> vector_unsigned_char {
@@ -4567,6 +4568,7 @@ pub unsafe fn vec_genmask<const MASK: u16>() -> vector_unsigned_char {
 /// Vector Generate Mask (Byte)
 #[inline]
 #[target_feature(enable = "vector")]
+#[rustc_legacy_const_generics(0, 1)]
 #[unstable(feature = "stdarch_s390x", issue = "135681")]
 #[cfg_attr(test, assert_instr(vrepib, L = 3, H = 5))]
 pub unsafe fn vec_genmasks_8<const L: u8, const H: u8>() -> vector_unsigned_char {
@@ -4576,6 +4578,7 @@ pub unsafe fn vec_genmasks_8<const L: u8, const H: u8>() -> vector_unsigned_char
 /// Vector Generate Mask (Halfword)
 #[inline]
 #[target_feature(enable = "vector")]
+#[rustc_legacy_const_generics(0, 1)]
 #[unstable(feature = "stdarch_s390x", issue = "135681")]
 #[cfg_attr(test, assert_instr(vrepih, L = 3, H = 5))]
 pub unsafe fn vec_genmasks_16<const L: u8, const H: u8>() -> vector_unsigned_short {
@@ -4585,6 +4588,7 @@ pub unsafe fn vec_genmasks_16<const L: u8, const H: u8>() -> vector_unsigned_sho
 /// Vector Generate Mask (Word)
 #[inline]
 #[target_feature(enable = "vector")]
+#[rustc_legacy_const_generics(0, 1)]
 #[unstable(feature = "stdarch_s390x", issue = "135681")]
 #[cfg_attr(test, assert_instr(vgmf, L = 3, H = 5))]
 pub unsafe fn vec_genmasks_32<const L: u8, const H: u8>() -> vector_unsigned_int {
@@ -4594,6 +4598,7 @@ pub unsafe fn vec_genmasks_32<const L: u8, const H: u8>() -> vector_unsigned_int
 /// Vector Generate Mask (Doubleword)
 #[inline]
 #[target_feature(enable = "vector")]
+#[rustc_legacy_const_generics(0, 1)]
 #[unstable(feature = "stdarch_s390x", issue = "135681")]
 #[cfg_attr(test, assert_instr(vgmg, L = 3, H = 5))]
 pub unsafe fn vec_genmasks_64<const L: u8, const H: u8>() -> vector_unsigned_long_long {
@@ -4810,6 +4815,7 @@ pub unsafe fn vec_subec_u128(
 /// Vector Splat Signed Byte
 #[inline]
 #[target_feature(enable = "vector")]
+#[rustc_legacy_const_generics(0)]
 #[unstable(feature = "stdarch_s390x", issue = "135681")]
 #[cfg_attr(test, assert_instr(vrepib, IMM = 42))]
 pub unsafe fn vec_splat_s8<const IMM: i8>() -> vector_signed_char {
@@ -4819,6 +4825,7 @@ pub unsafe fn vec_splat_s8<const IMM: i8>() -> vector_signed_char {
 /// Vector Splat Signed Halfword
 #[inline]
 #[target_feature(enable = "vector")]
+#[rustc_legacy_const_generics(0)]
 #[unstable(feature = "stdarch_s390x", issue = "135681")]
 #[cfg_attr(test, assert_instr(vrepih, IMM = 42))]
 pub unsafe fn vec_splat_s16<const IMM: i16>() -> vector_signed_short {
@@ -4828,6 +4835,7 @@ pub unsafe fn vec_splat_s16<const IMM: i16>() -> vector_signed_short {
 /// Vector Splat Signed Word
 #[inline]
 #[target_feature(enable = "vector")]
+#[rustc_legacy_const_generics(0)]
 #[unstable(feature = "stdarch_s390x", issue = "135681")]
 #[cfg_attr(test, assert_instr(vrepif, IMM = 42))]
 pub unsafe fn vec_splat_s32<const IMM: i16>() -> vector_signed_int {
@@ -4837,6 +4845,7 @@ pub unsafe fn vec_splat_s32<const IMM: i16>() -> vector_signed_int {
 /// Vector Splat Signed Doubleword
 #[inline]
 #[target_feature(enable = "vector")]
+#[rustc_legacy_const_generics(0)]
 #[unstable(feature = "stdarch_s390x", issue = "135681")]
 #[cfg_attr(test, assert_instr(vrepig, IMM = 42))]
 pub unsafe fn vec_splat_s64<const IMM: i16>() -> vector_signed_long_long {
@@ -4846,6 +4855,7 @@ pub unsafe fn vec_splat_s64<const IMM: i16>() -> vector_signed_long_long {
 /// Vector Splat Unsigned Byte
 #[inline]
 #[target_feature(enable = "vector")]
+#[rustc_legacy_const_generics(0)]
 #[unstable(feature = "stdarch_s390x", issue = "135681")]
 #[cfg_attr(test, assert_instr(vrepib, IMM = 42))]
 pub unsafe fn vec_splat_u8<const IMM: u8>() -> vector_unsigned_char {
@@ -4855,6 +4865,7 @@ pub unsafe fn vec_splat_u8<const IMM: u8>() -> vector_unsigned_char {
 /// Vector Splat Unsigned Halfword
 #[inline]
 #[target_feature(enable = "vector")]
+#[rustc_legacy_const_generics(0)]
 #[unstable(feature = "stdarch_s390x", issue = "135681")]
 #[cfg_attr(test, assert_instr(vrepih, IMM = 42))]
 pub unsafe fn vec_splat_u16<const IMM: i16>() -> vector_unsigned_short {
@@ -4864,6 +4875,7 @@ pub unsafe fn vec_splat_u16<const IMM: i16>() -> vector_unsigned_short {
 /// Vector Splat Unsigned Word
 #[inline]
 #[target_feature(enable = "vector")]
+#[rustc_legacy_const_generics(0)]
 #[unstable(feature = "stdarch_s390x", issue = "135681")]
 #[cfg_attr(test, assert_instr(vrepif, IMM = 42))]
 pub unsafe fn vec_splat_u32<const IMM: i16>() -> vector_unsigned_int {
@@ -4873,6 +4885,7 @@ pub unsafe fn vec_splat_u32<const IMM: i16>() -> vector_unsigned_int {
 /// Vector Splat Unsigned Doubleword
 #[inline]
 #[target_feature(enable = "vector")]
+#[rustc_legacy_const_generics(0)]
 #[unstable(feature = "stdarch_s390x", issue = "135681")]
 #[cfg_attr(test, assert_instr(vrepig, IMM = 42))]
 pub unsafe fn vec_splat_u64<const IMM: i16>() -> vector_unsigned_long_long {
@@ -5366,6 +5379,7 @@ pub unsafe fn vec_cp_until_zero_cc<T: sealed::VectorCopyUntilZeroCC>(a: T) -> (T
 /// Vector Multiply Sum Logical
 #[inline]
 #[target_feature(enable = "vector-enhancements-1")]
+#[rustc_legacy_const_generics(3)]
 #[unstable(feature = "stdarch_s390x", issue = "135681")]
 #[cfg_attr(
     all(test, target_feature = "vector-enhancements-1"),

crates/core_arch/src/wasm32/mod.rs

@@ -190,6 +190,7 @@ unsafe extern "C-unwind" {
 //        reenable this attribute.
 // #[cfg_attr(test, assert_instr(throw, TAG = 0, ptr = core::ptr::null_mut()))]
 #[inline]
+#[rustc_legacy_const_generics(1)]
 #[unstable(feature = "wasm_exception_handling_intrinsics", issue = "122465")]
 // FIXME: Since this instruction unwinds, `core` built with `-C panic=unwind`
 //        cannot be linked with `-C panic=abort` programs. But that's not