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22 changes: 22 additions & 0 deletions src/capability/mod.rs
Original file line number Diff line number Diff line change
Expand Up @@ -87,6 +87,28 @@ impl PciCapability {
_ => Some(PciCapability::Unknown { address, id }),
}
}

pub fn address(&self) -> PciCapabilityAddress {
match *self {
PciCapability::PowerManagement(address) => address,
PciCapability::AcceleratedGraphicsPort(address) => address,
PciCapability::VitalProductData(address) => address,
PciCapability::SlotIdentification(address) => address,
PciCapability::Msi(msi_cap) => msi_cap.address,
PciCapability::CompactPCIHotswap(address) => address,
PciCapability::PciX(address) => address,
PciCapability::HyperTransport(address) => address,
PciCapability::Vendor(address) => address,
PciCapability::DebugPort(address) => address,
PciCapability::CompactPCICentralResourceControl(address) => address,
PciCapability::PciHotPlugControl(address) => address,
PciCapability::BridgeSubsystemVendorId(address) => address,
PciCapability::AGP3(address) => address,
PciCapability::PciExpress(address) => address,
PciCapability::MsiX(msix_cap) => msix_cap.address,
PciCapability::Unknown { address, id: _ } => address,
}
}
}

pub struct CapabilityIterator<T: ConfigRegionAccess> {
Expand Down
2 changes: 1 addition & 1 deletion src/capability/msi.rs
Original file line number Diff line number Diff line change
Expand Up @@ -47,7 +47,7 @@ pub enum TriggerMode {

#[derive(Debug, Clone, Copy)]
pub struct MsiCapability {
address: PciCapabilityAddress,
pub(super) address: PciCapabilityAddress,
per_vector_masking: bool,
is_64bit: bool,
multiple_message_capable: MultipleMessageSupport,
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2 changes: 1 addition & 1 deletion src/capability/msix.rs
Original file line number Diff line number Diff line change
Expand Up @@ -4,7 +4,7 @@ use bit_field::BitField;

#[derive(Clone, Copy, Debug)]
pub struct MsixCapability {
address: PciCapabilityAddress,
pub(super) address: PciCapabilityAddress,
table_size: u16,
/// Table BAR in bits 0..3 and offset into that BAR in bits 3..31
table: u32,
Expand Down