This repository contains a five stage pipelined RISC-V (RV32IM) processor and multiple peripherals. The target FPGA is Intel (Altera) DE2-115.
Four peripherals are connected to the processor through Memory Mapped Input/Output (MMIO). Firstly, GPIO peripheral which controls the onboard 9 Green LEDs, 18 Red LEDs, 18 switches, and 8 7-Segment Displays. Secondly, the VGA peripheral which generate a video signal through the onboard VGA connector. Thirdly, LCD module which controls the LCD Display attached to the FPGA. Lastly, RS232 (UART) is connected to the processor as MMIO that allows communication with other devices. The Base address for the GPIO module is 0x8000_0000, while the base address space for the VGA is 0x4000_0000. The base address for the LCD module is 0x5000_0000, and the base address for the RS232 module is 0x6000_0000.
The Hardware Description Language (HDL) used in this repository is SystemVerilog 2012 Standard (IEEE1800-2012).
├── assembly <- Contains sample testing programs for the processor written in assembly.
├── rtl <- Contains SystemVerilog files of the processor and the peripherals.
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├── tb <- Contains test bench files for the stand alone processor and the top level module that includes the peripherals
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├── .svlint.toml <- SystemVerilog lint configuration file.
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├── Makefile <- Make file used to simulate and lint the system verilog files.
├── README.md <- The top-level README for developers using this project.
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├── rv32im.do <- Modelsim do file used to simulate the SystemVerilog files.
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└── yosys_syn <- yosys commands file used to synthesize SystemVerilog files.
This work is licensed under the GNU GENERAL PUBLIC LICENSE Version 3, which implies that you can freely share and adapt this content. To view a copy of this license, visit https://www.gnu.org/licenses/gpl-3.0.en.html .