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Merged
merged 6 commits into from
Sep 16, 2024
Merged

Drop Old Architectures #273

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7ef46d9
Drop support for Tilera architectures.
insertinterestingnamehere Sep 11, 2024
dafab3e
Drop support for Itanium.
insertinterestingnamehere Sep 12, 2024
692e6de
Drop whatever support is present for ALPHA architecture.
insertinterestingnamehere Sep 12, 2024
1a5f763
Drop whatever preliminary support was there for MIPS.
insertinterestingnamehere Sep 12, 2024
6d9ae78
Drop support for Sparc architecture.
insertinterestingnamehere Sep 12, 2024
d055ede
Stop searching for the old ia32intrin.h header.
insertinterestingnamehere Sep 12, 2024
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13 changes: 0 additions & 13 deletions README.md
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Expand Up @@ -169,16 +169,3 @@ use those compilers, you probably need to configure with

*******************************************************

## NOTE FOR TILERA USERS
The Tilera cache coherency protocols, as of the TileGX boards, appear to be
somewhat buggy for large multithreaded programs. And by buggy I mean they cause
kernel panics (at least, I haven't been able to demonstrate data corruption
yet). Thankfully, you can pick from several cache coherency protocols, and one
of them is more stable than the default. What I have found that seems to be
*more* stable, if not perfectly stable, is to force the cache coherency
protocol to hashed. The way you do this is with a boot argument to the Tilera
kernel. The tile-monitor command I use is this:

`tile-monitor --net <tilera> --hvx ucache_hash=all --`

Good luck!
57 changes: 0 additions & 57 deletions config/qthread_check_assembly.m4
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Expand Up @@ -79,30 +79,6 @@ unset qthread_assemble
])dnl


dnl #################################################################
dnl
dnl QTHREAD_CHECK_SPARCV8PLUS
dnl
dnl #################################################################
AC_DEFUN([QTHREAD_CHECK_SPARCV8PLUS],[
AC_MSG_CHECKING([if have Sparc v8+/v9 support])
sparc_result=0
QTHREAD_TRY_ASSEMBLE([$qthread_cv_asm_text
casa [%o0] 0x80, %o1, %o2],
[sparc_result=1],
[sparc_result=0])
if test "$sparc_result" = "1" ; then
AC_MSG_RESULT([yes])
ifelse([$1],,:,[$1])
else
AC_MSG_RESULT([no])
ifelse([$2],,:,[$2])
fi

unset sparc_result
])dnl


dnl #################################################################
dnl
dnl QTHREAD_CHECK_INLINE_GCC
Expand Down Expand Up @@ -179,23 +155,6 @@ AC_DEFUN([QTHREAD_CHECK_ASSEMBLY],[
qthread_gcc_inline_assign='"movl [$]0, %0" : "=&r"(ret)'
;;

ia64-*)
qthread_cv_asm_arch="IA64"
qthread_gcc_inline_assign='"mov %0=r0\n;;\n" : "=&r"(ret)'
;;

alpha-*|alphaev[[4-8]]-*|alphaev56-*|alphaev6[[78]]-*)
qthread_cv_asm_arch="ALPHA"
qthread_gcc_inline_assign='"bis [$]31,[$]31,%0" : "=&r"(ret)'
;;

tile-*)
AS_IF([test "$ac_cv_sizeof_long" = "4"],
[qthread_cv_asm_arch="TILE"],
[qthread_cv_asm_arch="TILEGX"])
qthread_gcc_inline_assign='"movei %0, 5" : "=&r"(ret)'
;;

armv7l-*)
qthread_cv_asm_arch="ARM"
qthread_gcc_inline_assign='"movt %0, #5" : "=&r"(ret)'
Expand All @@ -205,13 +164,6 @@ AC_DEFUN([QTHREAD_CHECK_ASSEMBLY],[
qthread_cv_asm_arch="ARMV8_A64"
;;

mips-*|mips64-*)
# Should really find some way to make sure that we are on
# a MIPS III machine (r4000 and later)
qthread_cv_asm_arch="MIPS"
qthread_gcc_inline_assign='"or %0,[$]0,[$]0" : "=&r"(ret)'
;;

powerpc*|powerpc64*)
AS_IF([test "$ac_cv_sizeof_long" = "4"],
[qthread_cv_asm_arch="POWERPC32"],
Expand All @@ -236,15 +188,6 @@ AC_DEFUN([QTHREAD_CHECK_ASSEMBLY],[
qthread_gcc_inline_assign='"A_%=: li %0,0" : "=&r"(ret)'
;;

sparc*-*)
# SPARC v9 (and above) are the only ones with 64bit support
# if compiling 32 bit, see if we are v9 (aka v8plus) or
# earlier (casa is v8+/v9).
AS_IF([test "$ac_cv_sizeof_long" = "4"],
[QTHREAD_CHECK_SPARCV8PLUS([qthread_cv_asm_arch="SPARCV9_32"])],
[qthread_cv_asm_arch="SPARCV9_64"])
qthread_gcc_inline_assign='"mov 0,%0" : "=&r"(ret)'
;;
esac

# now that we know our architecture, try to inline assemble
Expand Down
55 changes: 0 additions & 55 deletions config/qthread_check_atomics.m4
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Expand Up @@ -15,17 +15,9 @@ AS_IF([test "x$enable_builtin_atomics" != xno],
[AS_IF([test "x$enable_builtin_atomics" = xyes],
[AC_MSG_WARN([Disabling builtin atomics on IBM_XL, due to compiler design decision])])
enable_builtin_atomics=no])])
AS_IF([test "x$enable_builtin_atomics" != xno], [
AS_IF([test "x$qthread_cv_c_compiler_type" = xIntel -o "x$qthread_cv_cxx_compiler_type" = xIntel],
[AC_CHECK_HEADERS([ia64intrin.h ia32intrin.h])])
AC_CACHE_CHECK([whether compiler supports builtin atomic CAS-32],
[qthread_cv_atomic_CAS32],
[AC_LINK_IFELSE([AC_LANG_SOURCE([[
#ifdef HAVE_IA64INTRIN_H
# include <ia64intrin.h>
#elif HAVE_IA32INTRIN_H
# include <ia32intrin.h>
#endif
#include <stdlib.h>
#include <stdint.h> /* for uint32_t */

Expand All @@ -40,11 +32,6 @@ return (int)foo;
AC_CACHE_CHECK([whether compiler supports builtin atomic CAS-64],
[qthread_cv_atomic_CAS64],
[AC_LINK_IFELSE([AC_LANG_SOURCE([[
#ifdef HAVE_IA64INTRIN_H
# include <ia64intrin.h>
#elif HAVE_IA32INTRIN_H
# include <ia32intrin.h>
#endif
#include <stdlib.h>
#include <stdint.h> /* for uint64_t */

Expand All @@ -59,11 +46,6 @@ return foo;
AC_CACHE_CHECK([whether compiler supports builtin atomic CAS-ptr],
[qthread_cv_atomic_CASptr],
[AC_LINK_IFELSE([AC_LANG_SOURCE([[
#ifdef HAVE_IA64INTRIN_H
# include <ia64intrin.h>
#elif HAVE_IA32INTRIN_H
# include <ia32intrin.h>
#endif
#include <stdlib.h>

int main(void)
Expand Down Expand Up @@ -130,11 +112,6 @@ AC_CACHE_CHECK([whether compiler supports builtin atomic incr],
[qthread_cv_atomic_incr],
[AS_IF([test "$1" -eq 8],
[AC_LINK_IFELSE([AC_LANG_SOURCE([[
#ifdef HAVE_IA64INTRIN_H
# include <ia64intrin.h>
#elif HAVE_IA32INTRIN_H
# include <ia32intrin.h>
#endif
#include <stdlib.h>
#include <stdint.h> /* for uint64_t */

Expand All @@ -147,11 +124,6 @@ return foo;
[qthread_cv_atomic_incr="yes"],
[qthread_cv_atomic_incr="no"])],
[AC_LINK_IFELSE([AC_LANG_SOURCE([[
#ifdef HAVE_IA64INTRIN_H
# include <ia64intrin.h>
#elif HAVE_IA32INTRIN_H
# include <ia32intrin.h>
#endif
#include <stdlib.h>
#include <stdint.h> /* for uint32_t */

Expand All @@ -169,11 +141,6 @@ AS_IF([test "$qthread_cv_atomic_incr" = "yes"],
[qt_cv_atomic_incr_works],
[AS_IF([test "$1" -eq 8],
[AC_RUN_IFELSE([AC_LANG_SOURCE([[
#ifdef HAVE_IA64INTRIN_H
# include <ia64intrin.h>
#elif HAVE_IA32INTRIN_H
# include <ia32intrin.h>
#endif
#include <stdlib.h>
#include <stdint.h> /* for uint64_t */

Expand Down Expand Up @@ -204,11 +171,6 @@ return 0;
[qt_cv_atomic_incr_works="no"],
[qt_cv_atomic_incr_works="assuming yes"])],
[AC_RUN_IFELSE([AC_LANG_SOURCE([[
#ifdef HAVE_IA64INTRIN_H
# include <ia64intrin.h>
#elif HAVE_IA32INTRIN_H
# include <ia32intrin.h>
#endif
#include <stdlib.h>
#include <stdint.h> /* for uint32_t */

Expand All @@ -224,23 +186,6 @@ return 0;
[qt_cv_atomic_incr_works="no"],
[qt_cv_atomic_incr_works="assuming yes"])])
])])
AS_IF([test "$qthread_cv_atomic_CAS" = "yes"],
[AC_CACHE_CHECK([whether ia64intrin.h is required],
[qthread_cv_require_ia64intrin_h],
[AC_LINK_IFELSE([AC_LANG_SOURCE([[
#include <stdlib.h>

int main(void)
{
long bar=1, old=1, new=2;
long foo = __sync_val_compare_and_swap(&bar, old, new);
return foo;
}]])],
[qthread_cv_require_ia64intrin_h="no"],
[qthread_cv_require_ia64intrin_h="yes"])])])
])
AS_IF([test "$qthread_cv_require_ia64intrin_h" = "yes"],
[AC_DEFINE([QTHREAD_NEEDS_IA64INTRIN],[1],[if this header is necessary for builtin atomics])])
AS_IF([test "x$qthread_cv_atomic_CASptr" = "xyes"],
[AC_DEFINE([QTHREAD_ATOMIC_CAS_PTR],[1],
[if the compiler supports __sync_val_compare_and_swap on pointers])])
Expand Down
3 changes: 0 additions & 3 deletions config/qthread_check_attributes.m4
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Expand Up @@ -140,9 +140,6 @@ AC_CACHE_CHECK([support for __sync_synchronize],
POWERPC*)
mdefstr='__asm__ __volatile__ ("sync":::"memory")'
;;
SPARCV9_32|SPARCV9_64)
mdefstr='__asm__ __volatile__ ("membar #StoreStore|#LoadStore|#StoreLoad|#LoadLoad":::"memory")'
;;
*)
AC_MSG_ERROR([ASM $qthread_cv_asm_arch])
mdefstr="$cdefstr"
Expand Down
23 changes: 0 additions & 23 deletions config/qthread_check_tiletopo.m4
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This file was deleted.

8 changes: 0 additions & 8 deletions config/qthread_detect_compiler_type.m4
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Expand Up @@ -29,8 +29,6 @@ AC_CACHE_CHECK([what kind of C compiler $CC is],
[AC_LANG_PUSH([C])

dnl These compilers have been caught pretending to be GNU GCC
AS_IF([test "x$qthread_cv_c_compiler_type" == x],
[_QTHREAD_CHECK_IFDEF([__TILECC__],[qthread_cv_c_compiler_type=TileCC])])
AS_IF([test "x$qthread_cv_c_compiler_type" == x],
[_QTHREAD_CHECK_IFDEF([__INTEL_COMPILER],[qthread_cv_c_compiler_type=Intel])])
AS_IF([test "x$qthread_cv_c_compiler_type" == x],
Expand Down Expand Up @@ -141,8 +139,6 @@ AC_CACHE_CHECK([what kind of C compiler $CC is],
[_QTHREAD_CHECK_IFDEF([__HIGHC__],[qthread_cv_c_compiler_type=MetaWare])])
AS_IF([test "x$qthread_cv_c_compiler_type" == x],
[_QTHREAD_CHECK_IFDEF([__MWERKS__],[qthread_cv_c_compiler_type=MetrowerksCodeWarrior])])
AS_IF([test "x$qthread_cv_c_compiler_type" == x],
[_QTHREAD_CHECK_IFDEF([__sgi],[qthread_cv_c_compiler_type=MIPSpro])])
AS_IF([test "x$qthread_cv_c_compiler_type" == x],
[_QTHREAD_CHECK_IFDEF([__MRC__],[qthread_cv_c_compiler_type=MPW])])
AS_IF([test "x$qthread_cv_c_compiler_type" == x],
Expand Down Expand Up @@ -201,8 +197,6 @@ AC_CACHE_CHECK([what kind of C++ compiler $CXX is],
[AC_LANG_PUSH([C++])

dnl These compilers have been caught pretending to be GNU G++
AS_IF([test "x$qthread_cv_cxx_compiler_type" == x],
[_QTHREAD_CHECK_IFDEF([__TILECC__],[qthread_cv_cxx_compiler_type=TileCC])])
AS_IF([test "x$qthread_cv_cxx_compiler_type" == x],
[_QTHREAD_CHECK_IFDEF([__INTEL_COMPILER],[qthread_cv_cxx_compiler_type=Intel])])
AS_IF([test "x$qthread_cv_cxx_compiler_type" == x],
Expand Down Expand Up @@ -281,8 +275,6 @@ AC_CACHE_CHECK([what kind of C++ compiler $CXX is],
[_QTHREAD_CHECK_IFDEF([__HIGHC__],[qthread_cv_cxx_compiler_type=MetaWare])])
AS_IF([test "x$qthread_cv_cxx_compiler_type" == x],
[_QTHREAD_CHECK_IFDEF([__MWERKS__],[qthread_cv_cxx_compiler_type=MetrowerksCodeWarrior])])
AS_IF([test "x$qthread_cv_cxx_compiler_type" == x],
[_QTHREAD_CHECK_IFDEF([__sgi],[qthread_cv_cxx_compiler_type=MIPSpro])])
AS_IF([test "x$qthread_cv_cxx_compiler_type" == x],
[_QTHREAD_CHECK_IFDEF([__MRC__],[qthread_cv_cxx_compiler_type=MPW])])
AS_IF([test "x$qthread_cv_cxx_compiler_type" == x],
Expand Down
13 changes: 2 additions & 11 deletions config/qthread_ia_cacheline.m4
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Expand Up @@ -9,22 +9,14 @@ AC_CACHE_CHECK([for x86 cache line size],
#define QTHREAD_UNSUPPORTED 0
#define QTHREAD_IA32 1
#define QTHREAD_AMD64 2
#define QTHREAD_IA64 3
#define QTHREAD_ALPHA 4
#define QTHREAD_MIPS 5
#define QTHREAD_POWERPC32 6
#define QTHREAD_POWERPC64 7
#define QTHREAD_SPARCV9_32 8
#define QTHREAD_SPARCV9_64 9
#define QTHREAD_TILEPRO 10
#define QTHREAD_TILEGX 11
#define QTHREAD_ARM 12
#define QTHREAD_ARMV8_A64 13
],[
int op = 1, eax, ebx, ecx, edx, cachelinesize;
FILE *f;
#if QTHREAD_ASSEMBLY_ARCH == QTHREAD_IA32 || \
QTHREAD_ASSEMBLY_ARCH == QTHREAD_IA64
#if QTHREAD_ASSEMBLY_ARCH == QTHREAD_IA32
# ifdef __PIC__
__asm__("push %%ebx\n\t"
"cpuid\n\t"
Expand All @@ -45,8 +37,7 @@ __asm__("cpuid"
cachelinesize = 8*((ebx>>8)&0xff);
if (cachelinesize == 0) {
op = 2;
#if QTHREAD_ASSEMBLY_ARCH == QTHREAD_IA32 || \
QTHREAD_ASSEMBLY_ARCH == QTHREAD_IA64
#if QTHREAD_ASSEMBLY_ARCH == QTHREAD_IA32
__asm__("push %%ebx\n\t"
"cpuid\n\t"
"mov %%ebx, %1\n\t"
Expand Down
35 changes: 8 additions & 27 deletions configure.ac
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Expand Up @@ -294,11 +294,11 @@ AC_ARG_WITH([topology],
[AS_HELP_STRING([--with-topology=[[topologylib]]],
[specify which topology interface to use. Supported
interfaces include no, hwloc, hwloc_v2, binders, lgrp, libnuma,
libnumaV2, mach, plpa, sys, and, tilera.])],
libnumaV2, mach, plpa, and sys.])],
[AS_IF([test "x$with_topology" = xyes],
[with_topology=none_specified])
case "$with_topology" in
hwloc|binders|hwloc_v2|lgrp|libnuma|libnumaV2|mach|no|plpa|sys|tilera) ;;
hwloc|binders|hwloc_v2|lgrp|libnuma|libnumaV2|mach|no|plpa|sys) ;;
none_specified) ;;
*)
AC_MSG_ERROR([Unsupported topology library ($with_topology)])
Expand Down Expand Up @@ -327,8 +327,7 @@ AC_ARG_ENABLE([condwait-queue],
[force the use of a pthread condwait queue,
instead of a spin-based queue for inter-thread
communication (important if spinning shepherds
interfere with each other). Default enabled on
sparc/solaris, but default disabled elsewhere.])])
interfere with each other). Default disabled.])])

AC_ARG_ENABLE([third-party-benchmarks],
[AS_HELP_STRING([--enable-third-party-benchmarks],
Expand Down Expand Up @@ -402,16 +401,9 @@ dnl Test for this *before* AC_PROG_CC, to avoid getting the default CFLAGS
dnl However, that means we don't know a ton about this machine or this compiler
dnl yet, so we may have to reset it later.
AS_IF([test "x$enable_debugging" = xyes],
[case "$build_cpu" in dnl (
sparc)
CFLAGS="$CFLAGS -O0 -g3"
CXXFLAGS="$CXXFLAGS -O0 -g3"
;;
*)
CFLAGS="$CFLAGS -O0 -g"
CXXFLAGS="$CXXFLAGS -O0 -g"
;;
esac])
[CFLAGS="$CFLAGS -O0 -g"
CXXFLAGS="$CXXFLAGS -O0 -g"
])
AC_PROG_CC
dnl We use system extensions. This includes setting _GNU_SOURCE
AC_USE_SYSTEM_EXTENSIONS
Expand Down Expand Up @@ -495,7 +487,7 @@ AS_IF([test "x$enable_picky" = xyes],

QTHREAD_CHECK_ASSEMBLY([have_assembly=1], [have_assembly=0])
case "$qthread_cv_asm_arch" in
POWERPC32|SPARCV9_32)
POWERPC32)
compile_compat_atomic=yes
;;
esac
Expand Down Expand Up @@ -735,14 +727,7 @@ AS_IF([test "x$enable_oversubscription" = "xyes"],
AC_CHECK_FUNCS([sched_yield])])

AS_IF([test "x$enable_condwait_queue" = "x"],
[case "$host" in
sparc-sun-solaris*)
enable_condwait_queue="yes"
;;
*)
enable_condwait_queue="no"
;;
esac])
[enable_condwait_queue="no"])
AS_IF([test "x$enable_condwait_queue" = "xyes"],
[AC_DEFINE([QTHREAD_CONDWAIT_BLOCKING_QUEUE], [1], [use pthread-based condwait for lf queue])])

Expand Down Expand Up @@ -989,10 +974,6 @@ AS_IF([test "x$qthread_topo" != xno],
[qthread_topo=libnumaV2],
[AS_IF([test "x$qthread_topo" != xno],
[AC_MSG_ERROR([Specified topology library ($qthread_topo) does not work.])])])])
AS_IF([test "x$qthread_topo" = xno -o "x$qthread_topo" = xtilera],
[QTHREAD_CHECK_TILETOPO([qthread_topo=tilera],
[AS_IF([test "x$qthread_topo" != xno],
[AC_MSG_ERROR([Specified topology library ($qthread_topo) does not work.])])])])
# Third, check any others.
AS_IF([test "x$qthread_topo" = xno -o "x$qthread_topo" = xmach],
[QTHREAD_CHECK_MACHTOPO([qthread_topo=mach],
Expand Down
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