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Fix/ecdsa err Fix #344 #345
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58e27c8
add assertion that sign_data is valid
kunxian-xia ab1befd
fix pk endianess bug
zhenfeizhang 7a8b263
clean up
zhenfeizhang 89fafcd
address comments
zhenfeizhang ce93161
fix errors in the sign_data check
kunxian-xia 0f70fcc
Delete bench_params.rs
lispc 2b9cf3f
Merge branch 'scroll-stable' into fix/ecdsa_err
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Original file line number | Diff line number | Diff line change |
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@@ -10,15 +10,15 @@ use crate::evm_circuit::util::constraint_builder::BaseConstraintBuilder; | |
use crate::table::{KeccakTable, LookupTable, RlpTable, TxFieldTag, TxTable}; | ||
#[cfg(not(feature = "enable-sign-verify"))] | ||
use crate::tx_circuit::sign_verify::pub_key_hash_to_address; | ||
use crate::util::{random_linear_combine_word as rlc, SubCircuit, SubCircuitConfig}; | ||
use crate::util::{keccak, random_linear_combine_word as rlc, SubCircuit, SubCircuitConfig}; | ||
use crate::witness; | ||
use crate::witness::{RlpDataType, RlpTxTag, Transaction}; | ||
use bus_mapping::circuit_input_builder::keccak_inputs_sign_verify; | ||
#[cfg(not(feature = "enable-sign-verify"))] | ||
use eth_types::sign_types::{pk_bytes_le, pk_bytes_swap_endianness}; | ||
use eth_types::{ | ||
sign_types::SignData, | ||
{Field, ToLittleEndian, ToScalar}, | ||
ToAddress, {Field, ToLittleEndian, ToScalar}, | ||
}; | ||
#[cfg(not(feature = "enable-sign-verify"))] | ||
use ethers_core::utils::keccak256; | ||
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@@ -1675,6 +1675,31 @@ impl<F: Field> SubCircuit<F> for TxCircuit<F> { | |
.collect::<Result<Vec<SignData>, Error>>()?; | ||
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config.load_aux_tables(layouter)?; | ||
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// check if tx.caller_address == recovered_pk | ||
let recovered_pks = keccak_inputs_sign_verify(&sign_datas) | ||
.into_iter() | ||
.enumerate() | ||
.filter(|(idx, _)| { | ||
// each sign_data produce two inputs for hashing | ||
// pk -> pk_hash, msg -> msg_hash | ||
idx % 2 == 0 | ||
}) | ||
.map(|(_, input)| input) | ||
.collect::<Vec<_>>(); | ||
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for (pk, tx) in recovered_pks.into_iter().zip(self.txs.iter()) { | ||
let pk_hash = keccak(&pk); | ||
let address = pk_hash.to_address(); | ||
if address != tx.caller_address { | ||
log::error!( | ||
"pk address from sign data {:?} does not match the one from tx address {:?}", | ||
address, | ||
tx.caller_address | ||
) | ||
} | ||
} | ||
There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. suggest change to log::error! so the test tx_circuit_bad_address will not panic There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. fixed with 89fafcd |
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#[cfg(feature = "enable-sign-verify")] | ||
{ | ||
let assigned_sig_verifs = | ||
|
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Original file line number | Diff line number | Diff line change |
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@@ -386,8 +386,8 @@ impl<F: Field> SignVerifyChip<F> { | |
// it is fine to use a phase 1 gate here | ||
let (_pk, _, address) = ecdsa_chip.range.gate.inner_product( | ||
ctx, | ||
&powers_of_256_cells[0..20].to_vec(), | ||
&pk_hash_cells[12..].to_vec(), | ||
There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more.
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&powers_of_256_cells[..20].to_vec(), | ||
&pk_hash_cells[..20].to_vec(), | ||
)?; | ||
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let is_address_zero = ecdsa_chip.range.is_equal( | ||
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cool! and LGTM!