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[+] Update sv: implement target_cfg_pkg.sv file isntead of generic pa…
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…rameters of the soc_top module. Alignment with the systemc model
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sergeykhbr committed Nov 23, 2023
1 parent 5727704 commit 9f2ea9a
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Showing 27 changed files with 154 additions and 179 deletions.
11 changes: 0 additions & 11 deletions sv/prj/impl/asic/asic_top.sv
Original file line number Diff line number Diff line change
Expand Up @@ -213,17 +213,6 @@ iobuf_tech iosddat3 (

riscv_soc #(
.async_reset(async_reset),
.cpu_num(CFG_CPU_NUM),
.ilog2_nways(CFG_ILOG2_NWAYS),
.ilog2_lines_per_way(CFG_ILOG2_LINES_PER_WAY),
.dlog2_nways(CFG_DLOG2_NWAYS),
.dlog2_lines_per_way(CFG_DLOG2_LINES_PER_WAY),
.l2cache_ena(CFG_L2CACHE_ENA),
.l2log2_nways(CFG_L2_LOG2_NWAYS),
.l2log2_lines_per_way(CFG_L2_LOG2_LINES_PER_WAY),
.bootrom_log2_size(CFG_BOOTROM_LOG2_SIZE),
.sram_log2_size(CFG_SRAM_LOG2_SIZE),
.bootfile(CFG_BOOTROM_FILE_HEX),
.sim_uart_speedup_rate(sim_uart_speedup_rate)
) soc0 (
.i_sys_nrst (w_sys_nrst),
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28 changes: 0 additions & 28 deletions sv/prj/impl/asic/asic_top_pkg.sv
Original file line number Diff line number Diff line change
Expand Up @@ -17,32 +17,4 @@ package asic_top_pkg;

localparam bit async_reset = 0;

// @brief Number of processors in a system
// @details This value may be in a range 1 to CFG_TOTAL_CPU_MAX-1
localparam int CFG_CPU_NUM = 1;

// @brief Caches size parameters.
// @note Caches line size configured in river_cfg file and affects L1 memory bus width.
localparam int CFG_ILOG2_LINES_PER_WAY = 7; // I$ length: 7=16KB; 8=32KB; ..
localparam int CFG_ILOG2_NWAYS = 2; // I$ associativity. Default bits width = 2, means 4 ways

localparam int CFG_DLOG2_LINES_PER_WAY = 7; // D$ length: 7=16KB; 8=32KB; ..
localparam int CFG_DLOG2_NWAYS = 2; // D$ associativity. Default bits width = 2, means 4 ways

// @brief Enable/disable L2 caching. L2 can be enabled even in 1 CPU config
localparam int CFG_L2CACHE_ENA = 1;
localparam int CFG_L2_LOG2_NWAYS = 4;
localparam int CFG_L2_LOG2_LINES_PER_WAY = 9; // 7=16KB; 8=32KB; 9=64KB, ..

// Internal Boot ROM size:
localparam int CFG_BOOTROM_LOG2_SIZE = 16; // 16=64 KB (default); 17=128KB; ..

// Project relative HEX-file name to init boot ROM without .hex extension:
localparam CFG_BOOTROM_FILE_HEX = "../../../../examples/bootrom_tests/linuxbuild/bin/bootrom_tests";

// Internal SRAM block:
// - Increase memory map if need > 2MB FU740
// - Change bootloader stack pointer if need less than 512 KB
localparam int CFG_SRAM_LOG2_SIZE = 18; // 19=512 KB (KC705); 21=2 MB (ASIC); ..

endpackage: asic_top_pkg
48 changes: 48 additions & 0 deletions sv/prj/impl/asic/target_cfg_pkg.sv
Original file line number Diff line number Diff line change
@@ -0,0 +1,48 @@
//
// Copyright 2022 Sergey Khabarov, sergeykhbr@gmail.com
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
package target_cfg_pkg;



// @brief Number of processors in a system
// @details This value may be in a range 1 to CFG_TOTAL_CPU_MAX-1
localparam int CFG_CPU_NUM = 1;

// @brief Caches size parameters.
// @note Caches line size configured in river_cfg file and affects L1 memory bus width.
localparam int CFG_ILOG2_LINES_PER_WAY = 7; // I$ length: 7=16KB; 8=32KB; ..
localparam int CFG_ILOG2_NWAYS = 2; // I$ associativity. Default bits width = 2, means 4 ways

localparam int CFG_DLOG2_LINES_PER_WAY = 7; // D$ length: 7=16KB; 8=32KB; ..
localparam int CFG_DLOG2_NWAYS = 2; // D$ associativity. Default bits width = 2, means 4 ways

// @brief Enable/disable L2 caching. L2 can be enabled even in 1 CPU config
localparam int CFG_L2CACHE_ENA = 1;
localparam int CFG_L2_LOG2_NWAYS = 4;
localparam int CFG_L2_LOG2_LINES_PER_WAY = 9; // 7=16KB; 8=32KB; 9=64KB, ..

// Internal Boot ROM size:
localparam int CFG_BOOTROM_LOG2_SIZE = 16; // 16=64 KB (default); 17=128KB; ..

// Project relative HEX-file name to init boot ROM without .hex extension:
localparam CFG_BOOTROM_FILE_HEX = "../../../../examples/bootrom_tests/linuxbuild/bin/bootrom_tests";

// Internal SRAM block:
// - Increase memory map if need > 2MB FU740
// - Change bootloader stack pointer if need less than 512 KB
localparam int CFG_SRAM_LOG2_SIZE = 21; // 19=512 KB (KC705); 21=2 MB (ASIC); ..

endpackage: target_cfg_pkg
2 changes: 2 additions & 0 deletions sv/prj/impl/asic_sim/Makefile
Original file line number Diff line number Diff line change
Expand Up @@ -45,6 +45,7 @@ comp: prep clr_logs
@echo " START COMPILATION: "
@echo "==========================================================================================="

${SRUN} xmvlog ${VLOG_PARAMS_TB} ${INC} ${GLOBAL_DEFINE} ../asic/target_cfg_pkg.sv
${SRUN} xmvlog ${VLOG_PARAMS_TB} ${INC} ${GLOBAL_DEFINE} -f ${LISTS_HOME}/ambalib.f
${SRUN} xmvlog ${VLOG_PARAMS_TB} ${INC} ${GLOBAL_DEFINE} -f ${LISTS_HOME}/riverlib.f
${SRUN} xmvlog ${VLOG_PARAMS_TB} ${INC} ${GLOBAL_DEFINE} -f ${LISTS_HOME}/techmap.f
Expand Down Expand Up @@ -74,6 +75,7 @@ mce_flow: prep clr_logs
-timescale 1ns/10ps \
-access -rwc \
+UART_LOG_PATH=uart -input run.tcl ${VLOG_PARAMS_TB} ${INC} ${GLOBAL_DEFINE} \
../asic/target_cfg_pkg.sv \
-f ${LISTS_HOME}/ambalib.f \
-f ${LISTS_HOME}/riverlib.f \
-f ${LISTS_HOME}/techmap.f \
Expand Down
11 changes: 0 additions & 11 deletions sv/prj/impl/kc705/kc705_top.sv
Original file line number Diff line number Diff line change
Expand Up @@ -235,17 +235,6 @@ iobuf_tech iosddat3 (

riscv_soc #(
.async_reset(async_reset),
.cpu_num(CFG_CPU_NUM),
.ilog2_nways(CFG_ILOG2_NWAYS),
.ilog2_lines_per_way(CFG_ILOG2_LINES_PER_WAY),
.dlog2_nways(CFG_DLOG2_NWAYS),
.dlog2_lines_per_way(CFG_DLOG2_LINES_PER_WAY),
.l2cache_ena(CFG_L2CACHE_ENA),
.l2log2_nways(CFG_L2_LOG2_NWAYS),
.l2log2_lines_per_way(CFG_L2_LOG2_LINES_PER_WAY),
.bootrom_log2_size(CFG_BOOTROM_LOG2_SIZE),
.sram_log2_size(CFG_SRAM_LOG2_SIZE),
.bootfile(CFG_BOOTROM_FILE_HEX),
.sim_uart_speedup_rate(sim_uart_speedup_rate)
) soc0 (
.i_sys_nrst (w_sys_nrst),
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28 changes: 0 additions & 28 deletions sv/prj/impl/kc705/kc705_top_pkg.sv
Original file line number Diff line number Diff line change
Expand Up @@ -17,32 +17,4 @@ package kc705_top_pkg;

localparam bit async_reset = 0;

// @brief Number of processors in a system
// @details This value may be in a range 1 to CFG_TOTAL_CPU_MAX-1
localparam int CFG_CPU_NUM = 1;

// @brief Caches size parameters.
// @note Caches line size configured in river_cfg file and affects L1 memory bus width.
localparam int CFG_ILOG2_LINES_PER_WAY = 7; // I$ length: 7=16KB; 8=32KB; ..
localparam int CFG_ILOG2_NWAYS = 2; // I$ associativity. Default bits width = 2, means 4 ways

localparam int CFG_DLOG2_LINES_PER_WAY = 7; // D$ length: 7=16KB; 8=32KB; ..
localparam int CFG_DLOG2_NWAYS = 2; // D$ associativity. Default bits width = 2, means 4 ways

// @brief Enable/disable L2 caching. L2 can be enabled even in 1 CPU config
localparam int CFG_L2CACHE_ENA = 0;
localparam int CFG_L2_LOG2_NWAYS = 4;
localparam int CFG_L2_LOG2_LINES_PER_WAY = 9; // 7=16KB; 8=32KB; 9=64KB, ..

// Internal Boot ROM size:
localparam int CFG_BOOTROM_LOG2_SIZE = 16; // 16=64 KB (default); 17=128KB; ..

// Project relative HEX-file name to init boot ROM without .hex extension:
localparam CFG_BOOTROM_FILE_HEX = "../../../../examples/bootrom_tests/linuxbuild/bin/bootrom_tests";

// Internal SRAM block:
// - Increase memory map if need > 2MB FU740
// - Change bootloader stack pointer if need less than 512 KB
localparam int CFG_SRAM_LOG2_SIZE = 18; // 19=512 KB (KC705); 21=2 MB (ASIC); ..

endpackage: kc705_top_pkg
1 change: 1 addition & 0 deletions sv/prj/impl/kc705/run_nonproj_flow.tcl
Original file line number Diff line number Diff line change
Expand Up @@ -99,6 +99,7 @@ source -notrace scripts/set_paths.tcl

# Load project files if LOAD_FILES = true:
if {[string is true $load_files]} {
read_verilog -sv target_cfg_pkg.sv
set filelist_name ${LIST_ROOT}/ambalib.f; source -notrace scripts/get_file_list.tcl; read_verilog -sv [subst $filelist]
set filelist_name ${LIST_ROOT}/techmap.f; source -notrace scripts/get_file_list.tcl; read_verilog -sv [subst $filelist]
set filelist_name ${LIST_ROOT}/techmap_ddr_kc705.f; source -notrace scripts/get_file_list.tcl; read_verilog -sv [subst $filelist]
Expand Down
48 changes: 48 additions & 0 deletions sv/prj/impl/kc705/target_cfg_pkg.sv
Original file line number Diff line number Diff line change
@@ -0,0 +1,48 @@
//
// Copyright 2022 Sergey Khabarov, sergeykhbr@gmail.com
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
package target_cfg_pkg;



// @brief Number of processors in a system
// @details This value may be in a range 1 to CFG_TOTAL_CPU_MAX-1
localparam int CFG_CPU_NUM = 1;

// @brief Caches size parameters.
// @note Caches line size configured in river_cfg file and affects L1 memory bus width.
localparam int CFG_ILOG2_LINES_PER_WAY = 7; // I$ length: 7=16KB; 8=32KB; ..
localparam int CFG_ILOG2_NWAYS = 2; // I$ associativity. Default bits width = 2, means 4 ways

localparam int CFG_DLOG2_LINES_PER_WAY = 7; // D$ length: 7=16KB; 8=32KB; ..
localparam int CFG_DLOG2_NWAYS = 2; // D$ associativity. Default bits width = 2, means 4 ways

// @brief Enable/disable L2 caching. L2 can be enabled even in 1 CPU config
localparam int CFG_L2CACHE_ENA = 1;
localparam int CFG_L2_LOG2_NWAYS = 4;
localparam int CFG_L2_LOG2_LINES_PER_WAY = 9; // 7=16KB; 8=32KB; 9=64KB, ..

// Internal Boot ROM size:
localparam int CFG_BOOTROM_LOG2_SIZE = 16; // 16=64 KB (default); 17=128KB; ..

// Project relative HEX-file name to init boot ROM without .hex extension:
localparam CFG_BOOTROM_FILE_HEX = "../../../../examples/bootrom_tests/linuxbuild/bin/bootrom_tests";

// Internal SRAM block:
// - Increase memory map if need > 2MB FU740
// - Change bootloader stack pointer if need less than 512 KB
localparam int CFG_SRAM_LOG2_SIZE = 21; // 19=512 KB (KC705); 21=2 MB (ASIC); ..

endpackage: target_cfg_pkg
2 changes: 2 additions & 0 deletions sv/prj/impl/kc705_sim/Makefile
Original file line number Diff line number Diff line change
Expand Up @@ -46,6 +46,7 @@ comp: prep clr_logs
@echo " START COMPILATION: "
@echo "==========================================================================================="

${SRUN} xmvlog ${VLOG_PARAMS_TB} ${INC} ${GLOBAL_DEFINE} ../kc705/target_cfg_pkg.sv
${SRUN} xmvlog ${VLOG_PARAMS_TB} ${INC} ${GLOBAL_DEFINE} -f ${LISTS_HOME}/ambalib.f
${SRUN} xmvlog ${VLOG_PARAMS_TB} ${INC} ${GLOBAL_DEFINE} -f ${LISTS_HOME}/riverlib.f
${SRUN} xmvlog ${VLOG_PARAMS_TB} ${INC} ${GLOBAL_DEFINE} -f ${LISTS_HOME}/techmap.f
Expand Down Expand Up @@ -76,6 +77,7 @@ mce_flow: prep clr_logs
-timescale 1ns/10ps \
-access -rwc \
+UART_LOG_PATH=uart -input run.tcl ${VLOG_PARAMS_TB} ${INC} ${GLOBAL_DEFINE} \
../kc705/target_cfg_pkg.sv \
-f ${LISTS_HOME}/ambalib.f \
-f ${LISTS_HOME}/riverlib.f \
-f ${LISTS_HOME}/techmap.f \
Expand Down
32 changes: 8 additions & 24 deletions sv/rtl/riscv_soc.sv
Original file line number Diff line number Diff line change
Expand Up @@ -18,17 +18,6 @@

module riscv_soc #(
parameter bit async_reset = 1'b0,
parameter int unsigned cpu_num = 1,
parameter int unsigned ilog2_nways = 2, // I$ Cache associativity. Default bits width = 2, means 4 ways
parameter int unsigned ilog2_lines_per_way = 7, // I$ Cache length: 7=16KB; 8=32KB; ..
parameter int unsigned dlog2_nways = 2, // D$ Cache associativity. Default bits width = 2, means 4 ways
parameter int unsigned dlog2_lines_per_way = 7, // D$ Cache length: 7=16KB; 8=32KB; ..
parameter int unsigned l2cache_ena = 1,
parameter int unsigned l2log2_nways = 4, // L2$ Cache associativity. Default bits width = 4, means 16 ways
parameter int unsigned l2log2_lines_per_way = 9, // L2$ Cache length: 9=64KB;
parameter int unsigned bootrom_log2_size = 16, // 16=64 KB (default); 17=128KB; ..
parameter int unsigned sram_log2_size = 21, // 19=512 KB (KC705); 21=2 MB (ASIC); ..
parameter bootfile = "", // Project relative HEX-file name to init boot ROM without .hex extension
parameter int sim_uart_speedup_rate = 0 // simulation UART speed-up: 0=no speed up, 1=2x, 2=4x, etc
)
(
Expand Down Expand Up @@ -94,6 +83,7 @@ import types_bus1_pkg::*;
import river_cfg_pkg::*;
import sdctrl_cfg_pkg::*;
import types_river_pkg::*;
import target_cfg_pkg::*;
import riscv_soc_pkg::*;

axi4_master_out_type acpo;
Expand Down Expand Up @@ -149,14 +139,8 @@ axi2apb_bus1 #(

Workgroup #(
.async_reset(async_reset),
.cpu_num(cpu_num),
.ilog2_nways(ilog2_nways),
.ilog2_lines_per_way(ilog2_lines_per_way),
.dlog2_nways(dlog2_nways),
.dlog2_lines_per_way(dlog2_lines_per_way),
.l2cache_ena(l2cache_ena),
.l2log2_nways(l2log2_nways),
.l2log2_lines_per_way(l2log2_lines_per_way)
.cpu_num(CFG_CPU_NUM),
.l2cache_ena(CFG_L2CACHE_ENA)
) group0 (
.i_cores_nrst(i_sys_nrst),
.i_dmi_nrst(i_dbg_nrst),
Expand Down Expand Up @@ -186,8 +170,8 @@ Workgroup #(

axi_rom #(
.async_reset(async_reset),
.abits(bootrom_log2_size),
.filename(bootfile)
.abits(CFG_BOOTROM_LOG2_SIZE),
.filename(CFG_BOOTROM_FILE_HEX)
) rom0 (
.i_clk(i_sys_clk),
.i_nrst(i_sys_nrst),
Expand All @@ -200,7 +184,7 @@ axi_rom #(

axi_sram #(
.async_reset(async_reset),
.abits(sram_log2_size)
.abits(CFG_SRAM_LOG2_SIZE)
) sram0 (
.i_clk(i_sys_clk),
.i_nrst(i_sys_nrst),
Expand Down Expand Up @@ -327,8 +311,8 @@ apb_pnp #(
.async_reset(async_reset),
.cfg_slots(SOC_PNP_TOTAL),
.hwid(SOC_HW_ID),
.cpu_max(cpu_num),
.l2cache_ena(l2cache_ena),
.cpu_max(CFG_CPU_NUM),
.l2cache_ena(CFG_L2CACHE_ENA),
.plic_irq_max(SOC_PLIC_IRQ_TOTAL)
) pnp0 (
.i_clk(i_sys_clk),
Expand Down
1 change: 1 addition & 0 deletions sv/rtl/riscv_soc_pkg.sv
Original file line number Diff line number Diff line change
Expand Up @@ -22,6 +22,7 @@ import types_bus1_pkg::*;
import river_cfg_pkg::*;
import sdctrl_cfg_pkg::*;
import types_river_pkg::*;
import target_cfg_pkg::*;


// Hardware SoC Identificator.
Expand Down
13 changes: 3 additions & 10 deletions sv/rtl/riverlib/cache/cache_top.sv
Original file line number Diff line number Diff line change
Expand Up @@ -18,11 +18,7 @@

module CacheTop #(
parameter bit async_reset = 1'b0,
parameter bit coherence_ena = 1'b0,
parameter int unsigned ilog2_nways = 2, // I$ Cache associativity. Default bits width = 2, means 4 ways
parameter int unsigned ilog2_lines_per_way = 7, // I$ Cache length: 7=16KB; 8=32KB; ..
parameter int unsigned dlog2_nways = 2, // D$ Cache associativity. Default bits width = 2, means 4 ways
parameter int unsigned dlog2_lines_per_way = 7 // D$ Cache length: 7=16KB; 8=32KB; ..
parameter bit coherence_ena = 1'b0
)
(
input logic i_clk, // CPU clock
Expand Down Expand Up @@ -89,6 +85,7 @@ module CacheTop #(
);

import river_cfg_pkg::*;
import target_cfg_pkg::*;
import cache_top_pkg::*;

logic [CFG_CPU_ADDR_BITS-1:0] wb_i_req_ctrl_addr;
Expand Down Expand Up @@ -121,9 +118,7 @@ logic queue_full_o;
logic queue_nempty_o;

ICacheLru #(
.async_reset(async_reset),
.waybits(ilog2_nways),
.ibits(ilog2_lines_per_way)
.async_reset(async_reset)
) i1 (
.i_clk(i_clk),
.i_nrst(i_nrst),
Expand Down Expand Up @@ -155,8 +150,6 @@ ICacheLru #(

DCacheLru #(
.async_reset(async_reset),
.waybits(dlog2_nways),
.ibits(dlog2_lines_per_way),
.coherence_ena(coherence_ena)
) d0 (
.i_clk(i_clk),
Expand Down
1 change: 1 addition & 0 deletions sv/rtl/riverlib/cache/cache_top_pkg.sv
Original file line number Diff line number Diff line change
Expand Up @@ -16,6 +16,7 @@
package cache_top_pkg;

import river_cfg_pkg::*;
import target_cfg_pkg::*;

localparam int DATA_PATH = 0;
localparam int CTRL_PATH = 1;
Expand Down
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