Computer-Architecture

• Designed up a 32-bit register CPU which runs MIPS instruction set architecture (Assembly language) using Verilog HDL • Implemented 20+ MIPS instructions of I (immediate), J (jump), and R (register) types • Sped up the CPU by implementing the pipelining approach and designing the processor as a Mealy state machine so instructions only went to states necessary for execution. • Used a testbench in Verilog for exercising and verifying the functional correctness of the CPU logic.