RFC: Using FuseSoC for source management of ZeroSoC

[olofk]

This series adds FuseSoC descriptions for ZeroSoC and changes build.py to use FuseSoC for the FPGA flow. Some notes:

• This is an RFC. The changes in build.py are a bit invasive and are only enabled for the FPGA target right now. Would like to decide with you how to best incorporate this in the flow
• It replaces the whole OpenTitan UART core with a modified version instead of just the single uart_core file. From a FuseSoC perspective this is a cleaner approach
• To avoid needing the OpenTitan fork of FuseSoC we use pre-generated prim files that were already in zerosoc and replace the prim generator with a dummy script

Other than that I think this is good to go.

[nmoroze]

Thanks so much for writing up this proof-of-concept! We've decided to keep the upstream flow as-is for now, but if you want to maintain this as a fork I'd be happy to give input on it. I do recognize that this is well-suited to ZeroSoC given that it's built around IP that already has existing FuseSoC core definitions, but for now we want to focus this repo on demonstrating how to interface with the SC schema directly.

I do think the best direction for this sort of integration would be to add an importer function analogous to read_manifest(), as you suggested in SC issue #784. For that, I think we can follow up discussion there!

[olofk]

It was a good exercise to get a feeling for the conceptual similarities between Edalize and SiliconCompiler but I understand if you want to keep this reference project without external dependencies. I'll probably do a write-up and make a zerosoc-like repo own my own to demonstrate how to expand FuseSoC-based projects to use more ASIC flows through SiliconCompiler