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phaser2 features #2

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7 of 19 tasks
jordens opened this issue Sep 26, 2016 · 7 comments
Closed
7 of 19 tasks

phaser2 features #2

jordens opened this issue Sep 26, 2016 · 7 comments

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@jordens
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jordens commented Sep 26, 2016

These are beyond the items in #1 and would be developed on the final hardware. Individual items will be split out into separate issues and referenced here when imminent.

Short term:

  • Absolute and relative phase modes for all frequency and phase interpolators independently configurable through RTIO
  • f,p,a,u modulation by RTIO (eDRTIO) for all interpolators
  • DMA DMA for pulse sequences m-labs/artiq#553
  • distributed DMA
  • Parallelizing CIC interpolator/AA filter before parallelized DDS core
  • Parallelized FIR filter after CIC, research and implement what’s possible given DSP resources
  • Coherent phase mode (implemented in kernel API and runtime) for frequency/phase updates of the three eDRTIO channels
  • gate-able counter TTL input RTIO channel High-speed TTL input counter m-labs/artiq#564

Longer term:

  • Time stretcher for interpolators to extend dynamic range beyond spline knot durations of 2**16 cycles
  • Saturating summing junctions
  • f,p,a,u modulation by external data stream (ePID) for all interpolators
  • Summing junction clipping detectors and their remote readout
  • Configurable, saturating output limiters
  • Monitoring support for all spline interpolators and total DAC output
  • Injection/override support for all spline interpolators
  • Distributed hardware logic analyzer support for all interpolators and DAC output
  • ADC support (ARTIQ, gateware, some DSP)
  • ADC burst acquisition via DRTIO
  • PID https://github.com/jordens/redpid https://github.com/nist-ionstorage/digital-servo digital servo (PID) #24
@dhslichter
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For confirmation: will DMA as listed above include the streaming of precompiled DAC samples from memory onto the DACs vias JESD204B? This would allow for sequences that may not be able to be created efficiently by the gateware CORDIC+interpolators (e.g. 20 ns duration Gaussian pulse at 1 GSPS). Will DMA be able to seamlessly take over streaming of DAC samples from CORDIC+interpolators, and then seamlessly return it? Use case would be to output a fixed dc level ("off" to a mixer IF port), then briefly stream in a complex/high-speed pulse such as above, then return to fixed dc level (again, "off" to a mixer IF port).

@jordens
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jordens commented Sep 27, 2016

Not currently. And DMA is functionally orthogonal to sample-based operation.
If somebody is interested in this (or other additional features), please open new issues.

@jbqubit jbqubit added this to the 0.1 board support milestone Feb 1, 2017
@jbqubit
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jbqubit commented Feb 1, 2017

@jordens please remove for-contract label since this is funded by ARL

@jordens
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jordens commented Feb 1, 2017

@jbqubit not all of it.

@jbqubit
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jbqubit commented Feb 1, 2017

@jordens Please annotate which parts are not funded.

@jordens
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jordens commented Feb 1, 2017

@jbqubit that's not wise and would be redundant. the individual tracking issues should also track their funding status.

@jbqubit jbqubit changed the title dsp/gateware features phaser2 features Feb 13, 2017
@jordens jordens self-assigned this Jul 17, 2017
@hartytp hartytp closed this as completed Aug 10, 2017
@jbqubit
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jbqubit commented Aug 11, 2017

Closed since gateware Issues migrated to ARTIQ. See

https://github.com/m-labs/artiq/labels/area%3Aphaser

and

https://github.com/m-labs/artiq/labels/area%3Asayma

@jordens jordens mentioned this issue Jan 15, 2018
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