Minutes20190111 Sayma v2
Agenda for Friday discussion. Name calls out who added item to agenda.
Time: 2019-01-11 14:00 UTC Venue: google hangouts
1400-1405 MC: administrative start
- Discuss minutes from last meeting, vote to accept/reject (https://github.com/sinara-hw/sinara/wiki/Minutes20181220-Sayma-v2)
- Option: Vote to extend agenda item time in 5 minute increments?
1405-1415 Jordens: proposal to do a stub port of ARTIQ to Sayma v2, on paper clock review
- see MT22 in Project Plan diff link below
1415-1420 Britton: Oxford report on phase determinism of ADF4356 (Sayma_RTM #3)
1420-1425 Jordens: discuss M-Labs proposed modifications to Project Plan.
- Britton & M-Labs have discussed project plan extensively since Dec 26
- M-Labs would like to see quite a few changes
- Here's a URL showing the proposed diffs: http://www.mergely.com/zybbobXk/
- Viewing is better with re-flow turned on
- Note that M-Labs has not yet had an opportunity to review these diffs so errors of omission, misunderstanding are mine
1425-1430 Britton: discuss design review underway
- each Developer: comment on sticking points or unforeseen dependencies
- contention: Britton doesn't know how to reconcile requests to freeze the design with well motivated but invasive requests to change the design.
- case in point 1: (HMC830 and ADF4356) vs (ADF4356 only)
- case in point 2: WR on RTM and addition of ARTIQ support
1430-1435 MC: administrative wrap up - bi-weekly written progress reports are expected for Developers. So far they've been missed. If this is retained due dates are 14th and 28th of the month. - designate next meeting's MC - designate next meeting minutes-taker - feedback on meeting quality
People: Joe Britton, Robert Jordens, Anna Kamińska, Paweł Kulik, Greg Kasprowicz, Tom Harty
Minutes: Paweł
- Stub design: M-labs would like to get netlists, DRTIO on RTM will proceed in parallel with this stub design.
- Paper clock review: some kind of report would be useful after report for future reference.
- Tom still needs more time to verify ADF4356 design and measurements. Next week there will be results.
- Discussion about changes proposed by M-labs postponed.
- RTM FPGA: -3 speedgrade needed, CTI needs final choice of the FPGA as soon as it's made to order it
- We'll leave HMC830 in the clock tree with ADF as primary chip with ADCLK948 as mux between them.
- RTM will have WR circuitry (same as AMC)
- Tom will consolidate tests of WR and all current data that is scattered (code, diagrams, measurements) and post it.
- Paweł should do a writeup of WR on AMC and RTM for Tom to check during design review.
- Bi-weekly progress reports dropped in favour of github and teleconferences.
- Next meeting's MC: Robert
- Next meeting minute-taker: Joe
(more detailed and raw notes below)
- Discuss minutes from last meeting, vote to accept/reject
(https://github.com/sinara-hw/sinara/wiki/Minutes20181220-Sayma-v2)
- Option: Vote to extend agenda item time in 5 minute increments?
Robert: minutes were surprisingly short compared to meeting time, eg.: no info on hardware reviews
Minutes are accepted.
Robert: To ensure that there are no roadblocks with gateware, M-labs would like to get netlists, even right now, port Artiq with this netlist (and sdram, uart etc.), to ensure that there are no errors, that Vivado can catch (e.g. voltage standards, clocking regions, conflicting standards).
DRTIO on RTM will proceed in parallel with this stub design.
Tom: Getting DRTIO on RTM is valuable now, to test on current hardware even if it's a hack.
On paper clock review:
M-labs would like to sign off that they can implement everything that is asked of them (once design is stable). Clock tree cannot be verified with stub, M-labs would check the clock schematics and how it's supposed to work.
How? IRC, but there should be also reference for the future, report of some kind? (undecided AFAICT)
Tom still needs more time to verify everything. Next week there will be results.
- Here's a URL showing the proposed diffs: http://www.mergely.com/zybbobXk/
M-labs would like a stress test in HT3. Creotech needs more time to discuss these changes internally, will discuss it next week.
- each Developer: comment on sticking points or unforeseen dependencies
Paweł: we need to decide and make a feature freeze before proceeding with design review of clocks.
FPGA choice (15T-> 35T/50T?):
We stick with 35, 50 is hard to get. 15->35 is <15 EUR more per chip. M-labs is not certain if 35 will be enough, but will investigate further options to fit on 35, Sebastien will need to sign off on that (needs speed and memory) -3 speedgrade needed if 35 (Greg said that -3 is hard to get, no clear conclusion) CTI needs final choice of the FPGA as soon as it's made to order it.
Greg left the meeting.
- contention: Britton doesn't know how to reconcile requests to freeze the design with well motivated but invasive requests to change the design.
-
case in point 1: (HMC830 and ADF4356) vs (ADF4356 only)
We'll leave HMC830 in the clock tree with ADF as primary chip with ADCLK as mux
But this adds tests to do, Tom suggested to omit testing HMC830
-
case in point 2: WR on RTM and addition of ARTIQ support
RTM will have WR circuitry
Everyone seems fine with design changes, as long as they are also checked during design review.
Tom will consolidate tests of WR and all current data that is scattered (code, diagrams, measurements) and post it.
Paweł should do a writeup of WR on AMC and RTM for Tom to check during design review.
Should m-labs do also the review? (didn't catch that)
M-labs and creotech should add tests for WR if we include it - CTI will discuss it on Monday.
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Original issue of freeze design vs. make a change wasn't discussed, but it seems, that these were last high-level requests (Paweł).
-
bi-weekly written progress reports are expected for Developers.
Github, hangout teleconferences instead to keep everyone up to date.
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designate next meeting's MC
Robert
-
designate next meeting minutes-taker
Joe
-
feedback on meeting quality
Robert: More efficient than last one, we're on the right track.