-
Notifications
You must be signed in to change notification settings - Fork 7
Minutes20190118 Sayma v2
Chair: Robert Minutes: Joe Present: Robert, Joe, Pawel, Greg, Anna
-
- Accept previous minutes: https://github.com/sinara-hw/sinara/wiki/Minutes20190111-Sayma-v2
-
- Status of Tom's ADF PLL tests
-
- Status of DRTIO on Sayma_RTM
-
- Status of ARTIQ stub port to Sayma v2 and clock tree review
-
- Next meeting chair, rough date, minutes taker.
Link to previous minutes. Pawel updated these minutes to reflect M-Labs request for -3 speed grade. With this edit there was no objection to last minutes.
Tom was not available for call.
RJ reports for SB.
- SB tested using Sayma v1.0 hardware. Transceiver link from AMC to RTM FPGAs via SATA cable. Bitstream builds at 150 MHz targeting -3 speed grade. SB tested RTIO synchronization on existing hardware (not -3 speed grade) and found it worked fine. Note that timing is not met in Vivado without calling for -3 speed grade. So it might be luck that the test worked on existing v1.0 hardware.
Regarding size choice of RTM FPGA. 35T and 50T are the same silicon but with different package labeling from Xilinx. RJ wrote a trick to use full Si. Risks of this hack to get more FPGA resources include the following.
- Xilinx might not have tested the "unapproved" silicon.
- Likely no tech support from Xilinx for this unapproved use.
Conclusion: Everyone on call is satisfied with choice of 35T-3. No change of course.
SB also looked into having many simultaneous DRTIO links from Metlino. When compiling gateware for 8 links on UltraScale master there's a problem. This is being discussed with Xilinx.
FPGA Pin list from Greg is being converted to stub port for Sayma.
M-Labs started looking at clock tree. But not yet complete.
SB reports 3.3V bug on Sayma v1.0. But getting additional Sayma v1.0 hardware from UMD isn't warranted.
Joe pointed out that a quote is still needed from M-Labs. Joe and Robert will discuss after the call ends.
Next chair: Pawel Next minutes: Robert Date: 28th or 29th