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fix: USB configuration STM32H723ZG #1932

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Merged
merged 3 commits into from
Jan 27, 2023
Merged

fix: USB configuration STM32H723ZG #1932

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e900175
fix: some STM32 mcu have only USB_OTG_HS available
fpistm Jan 26, 2023
dd2385f
fix: peripheral clock configuration for STM32H723ZGT
fpistm Jan 26, 2023
bec0296
chore: configure the clock recovery system for STM32H723ZGT
fpistm Jan 26, 2023
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4 changes: 4 additions & 0 deletions cores/arduino/stm32/usb/usbd_conf.h
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Original file line number Diff line number Diff line change
Expand Up @@ -35,6 +35,10 @@ extern "C" {
#if defined(USE_USB_HS) && !defined(USB_OTG_HS)
#error "This board does not support USB High Speed! Select 'Full Speed' in the 'Tools->USB interface' menu"
#endif
#if !defined(USB_BASE) && !defined(USB_OTG_FS) && defined(USB_OTG_HS) && !defined(USE_USB_HS)
#error "This board support only USB High Speed! Select 'High Speed' or 'High Speed in Full Speed mode' in the 'Tools->USB interface' menu"
#endif


#include <stdio.h>
#include <stdlib.h>
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41 changes: 41 additions & 0 deletions variants/STM32H7xx/H723Z(E-G)T_H730ZBT_H733ZGT/generic_clock.c
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Original file line number Diff line number Diff line change
Expand Up @@ -23,6 +23,8 @@ WEAK void SystemClock_Config(void)
{
RCC_OscInitTypeDef RCC_OscInitStruct = {};
RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {};
RCC_CRSInitTypeDef RCC_CRSInitStruct = {};

/** Supply configuration update enable
*/
Expand Down Expand Up @@ -71,5 +73,44 @@ WEAK void SystemClock_Config(void)
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) {
Error_Handler();
}

/** Initializes the peripherals clock
*/
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SDMMC | RCC_PERIPHCLK_USB;
PeriphClkInitStruct.PLL2.PLL2M = 32;
PeriphClkInitStruct.PLL2.PLL2N = 96;
PeriphClkInitStruct.PLL2.PLL2P = 2;
PeriphClkInitStruct.PLL2.PLL2Q = 2;
PeriphClkInitStruct.PLL2.PLL2R = 4;
PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2VCIRANGE_1;
PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2VCOWIDE;
PeriphClkInitStruct.PLL2.PLL2FRACN = 0.0;
PeriphClkInitStruct.SdmmcClockSelection = RCC_SDMMCCLKSOURCE_PLL2;
PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
Error_Handler();
}

/*Configure the clock recovery system (CRS)**********************************/

/*Enable CRS Clock*/
__HAL_RCC_CRS_CLK_ENABLE();

/* Default Synchro Signal division factor (not divided) */
RCC_CRSInitStruct.Prescaler = RCC_CRS_SYNC_DIV1;

/* Set the SYNCSRC[1:0] bits according to CRS_Source value */
RCC_CRSInitStruct.Source = RCC_CRS_SYNC_SOURCE_USB1;

/* HSI48 is synchronized with USB SOF at 1KHz rate */
RCC_CRSInitStruct.ReloadValue = RCC_CRS_RELOADVALUE_DEFAULT;
RCC_CRSInitStruct.ErrorLimitValue = RCC_CRS_ERRORLIMIT_DEFAULT;
RCC_CRSInitStruct.Polarity = RCC_CRS_SYNC_POLARITY_RISING;

/* Set the TRIM[5:0] to the default value */
RCC_CRSInitStruct.HSI48CalibrationValue = RCC_CRS_HSI48CALIBRATION_DEFAULT;

/* Start automatic synchronization */
HAL_RCCEx_CRSConfig(&RCC_CRSInitStruct);
}
#endif /* ARDUINO_GENERIC_* */
41 changes: 41 additions & 0 deletions variants/STM32H7xx/H723Z(E-G)T_H730ZBT_H733ZGT/variant_NUCLEO_H723ZG.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -183,6 +183,8 @@ WEAK void SystemClock_Config(void)
{
RCC_OscInitTypeDef RCC_OscInitStruct = {};
RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {};
RCC_CRSInitTypeDef RCC_CRSInitStruct = {};

/** Supply configuration update enable
*/
Expand Down Expand Up @@ -230,6 +232,45 @@ WEAK void SystemClock_Config(void)
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) {
Error_Handler();
}

/** Initializes the peripherals clock
*/
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SDMMC | RCC_PERIPHCLK_USB;
PeriphClkInitStruct.PLL2.PLL2M = 1;
PeriphClkInitStruct.PLL2.PLL2N = 24;
PeriphClkInitStruct.PLL2.PLL2P = 2;
PeriphClkInitStruct.PLL2.PLL2Q = 2;
PeriphClkInitStruct.PLL2.PLL2R = 4;
PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2VCIRANGE_3;
PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2VCOWIDE;
PeriphClkInitStruct.PLL2.PLL2FRACN = 0;
PeriphClkInitStruct.SdmmcClockSelection = RCC_SDMMCCLKSOURCE_PLL2;
PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
Error_Handler();
}

/*Configure the clock recovery system (CRS)**********************************/

/*Enable CRS Clock*/
__HAL_RCC_CRS_CLK_ENABLE();

/* Default Synchro Signal division factor (not divided) */
RCC_CRSInitStruct.Prescaler = RCC_CRS_SYNC_DIV1;

/* Set the SYNCSRC[1:0] bits according to CRS_Source value */
RCC_CRSInitStruct.Source = RCC_CRS_SYNC_SOURCE_USB1;

/* HSI48 is synchronized with USB SOF at 1KHz rate */
RCC_CRSInitStruct.ReloadValue = RCC_CRS_RELOADVALUE_DEFAULT;
RCC_CRSInitStruct.ErrorLimitValue = RCC_CRS_ERRORLIMIT_DEFAULT;
RCC_CRSInitStruct.Polarity = RCC_CRS_SYNC_POLARITY_RISING;

/* Set the TRIM[5:0] to the default value */
RCC_CRSInitStruct.HSI48CalibrationValue = RCC_CRS_HSI48CALIBRATION_DEFAULT;

/* Start automatic synchronization */
HAL_RCCEx_CRSConfig(&RCC_CRSInitStruct);
}

#ifdef __cplusplus
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