Reorder win-checks to improve performance #20
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Reorder win-check logic to favor row-wise over column-wise checks. This aligns better with C’s row-major memory layout, enhancing spatial locality. It reduces cache line crossings, cuts down total instruction count, and improves sequential memory access— especially useful for large boards or frequent evaluations. Benchmark on a 5×5 board (1M iterations): - Instructions: 20,042,179,354 → 9,528,171,690 (-52.5%) - Cache refs: 205,075 → 115,548 (-43.65%) - Cache misses: 28,503 → 20,176 (-29.23%) - Time elapsed: 0.971s → 0.597s (-38.5%) Despite a minor rise in miss rate, total misses declined due to fewer cache references.
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Reorder win-check logic to favor row-wise over column-wise checks. This aligns better with C’s row-major memory layout, enhancing spatial locality. It reduces cache line crossings, cuts down total instruction count, and improves sequential memory access— especially useful for large boards or frequent evaluations.
Benchmark on a 5×5 board (1M iterations):
Despite a minor rise in miss rate, total misses declined due to fewer cache references.