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Merged
merged 7 commits into from
Jan 24, 2022
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xiaohan484
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@xiaohan484 xiaohan484 commented Jan 19, 2022

This work integrate riscv-arch-test with I,M,C,Zifencei,privilege to
rv32emu-next.Use make compliance to do compliance test with specific
extension test or test case.

Note: rv32emu-next has passed all test in I,M,Zifencei,
only c.ebreak fail in C and 9 tests fail in privilege.

Co-authored-by: YuJen-Lin qscesz871107@gmail.com

@jserv jserv requested a review from eecheng87 January 19, 2022 08:48
@jserv jserv mentioned this pull request Jan 20, 2022
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Improve the writing!

@xiaohan484 xiaohan484 force-pushed the compliance-test branch 2 times, most recently from 7b71a15 to 1e20e49 Compare January 21, 2022 05:54
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The co-author should be YuJen-Lin <qscesz871107@gmail.com>

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Fix wording

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jserv commented Jan 21, 2022

Note: rv32emu-next has passed all test in I,M,Zifencei, only c.ebreak fail in C and 9 tests fail in privilege.

Improve the descriptions about test results for current ISA coverage.

@xiaohan484 xiaohan484 force-pushed the compliance-test branch 2 times, most recently from 75bfc1e to c90bbdb Compare January 23, 2022 07:16
xiaohan484 and others added 6 commits January 24, 2022 09:47
This work integrate riscv-arch-test with I,M,C,Zifencei,privilege to
rv32emu-next.Use `make compliance` to do compliance test with specific
extension test or test case.

Current progress of this emulator in riscv-arch-test(RV32):
* Passed Tests
    - `I`: Base Integer Instruction Set
    - `M`: Standard Extension for Integer Multiplication and Division
    - `Zifencei`: Instruction-Fetch Fence
* Failed Tests
    - `C`: Standard Extension for Compressed Instruction
        + `cebreak`
    - `privilege`: RISCV Privileged Specification
        + 2 system call
            * `ebreak`
            * `ecall`
        + 5 misaligned CB-type instructions
            * `misalign-beq`
            * `misalign-bge`
            * `misalign-bgeu`
            * `misalign-blt`
            * `misalign-bltu`
        + 1 misaligned CL-type instructions
            * `misalign-lw`
        + 1 misaligned CS-type instructions
            * `misalign-sw`
* Unsupported tests
    - `F` Standard Extension for Single-Precision Floating-Point

Co-authored-by: YuJen-Lin <qscesz871107@gmail.com>
Revise the grammar of the riscv-arch-test description and replace the
"compliance" to "arch-test".
@jserv jserv merged commit ac23963 into sysprog21:master Jan 24, 2022
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jserv commented Jan 24, 2022

Thank @xiaohan484 and @sammer1107 for contributing!

vestata pushed a commit to vestata/rv32emu that referenced this pull request Jan 24, 2025
This patch integrated riscv-arch-test with RV32{I,M,C,Zifencei,privilege}.
Run "make arch-test" to launch the comprehensive test suite with specific
extensions.

Current results:
* Passed Tests
    - I: Base Integer Instruction Set
    - M: Standard Extension for Integer Multiplication and Division
    - Zifencei: Instruction-Fetch Fence
* Failed Tests
    - C: Standard Extension for Compressed Instruction
        + cebreak
    - privilege: RISCV Privileged Specification
        + 2 system calls
            * ebreak
            * ecall
        + 5 misaligned CB-type instructions
            * misalign-beq
            * misalign-bge
            * misalign-bgeu
            * misalign-blt
            * misalign-bltu
        + 1 misaligned CL-type instructions
            * misalign-lw
        + 1 misaligned CS-type instructions
            * misalign-sw
* Unsupported tests
    - F Standard Extension for Single-Precision Floating-Point

Co-authored-by: YuJen-Lin <qscesz871107@gmail.com>
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2 participants