SGI Indy recreated at RTL level?

[Randrianasulu]

https://web.archive.org/web/20261102050432/https://www.linkedin.com/posts/ifinder_a-minor-personal-project-update-one-thing-activity-7436619486402834432-_nVn

Ian Finder at linkedin:

Video: my complete SGI Indigo gateware design, booting into the PROM under RTL simulation. Synthesis into an actual FPGA "Indigo-on-a-Chip" design, soon.

https://web.archive.org/web/20261102051617/https://www.linkedin.com/posts/ifinder_six-months-ago-i-mentioned-a-personal-project-activity-7492787715801772032-OW7O

Six months ago I mentioned a personal project of mine to reverse engineer and re-develop the entire SiliconGraphics Indigo R4000 workstation– a top of the line desktop computer from 1993– as a complete set of RTL blocks. Not an emulator. Effectively, a chip design. This required implementing the full 8-stage R4000 CPU (a lot more logic than the “academic” 5-stage MIPS R2K/3K demonstrator designs many of us played with in school), secondary caches, TLB, FPU, LG1 graphics, a 56000 DSP, WD93 SCSI [to SD], SEEQ ethernet controller, and SGI HPC1 ASIC in RTL from scratch– which I did using a mix of agentic AI, traditional co-simulation techniques, automated logic analysis against an original target, a lot of Verilator, and a little good old fashioned home-brew magic. Today, my silly project said a full "hello world" and booted all the way to the Indigo Magic Desktop with X11 and graphics on a real FPGA with an HDMI monitor attached.

Cool!

There is already open-source Indy FPGA project for MiSTeR

https://github.com/MiSTer-devel/SGIIndy_MiSTer

I hope at least some of those multicard designs from early SGI machines will be "immortalized" this way?

Silly wish of course.

PS:
https://github.com/starfrost013/motion
Early m68K based SGI machines apparently used 14 AMD bit-slice processors as "geometry engine" ....

And RealityEngine used i860 variants + custom hw.