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Merge pull request #36 from ewenmcneill/update-submodules-2018-08-27
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Update third party submodules (including edid-decode)
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mithro committed Aug 27, 2018
2 parents 4a97842 + 9916c81 commit 4a08835
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Showing 11 changed files with 11 additions and 11 deletions.
2 changes: 1 addition & 1 deletion .gitmodules
Original file line number Diff line number Diff line change
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url = https://github.com/enjoy-digital/litevideo.git
[submodule "third_party/edid-decode"]
path = third_party/edid-decode
url = https://anongit.freedesktop.org/git/xorg/app/edid-decode
url = https://git.linuxtv.org/edid-decode.git/
[submodule "third_party/flash_proxies"]
path = third_party/flash_proxies
url = https://github.com/jordens/bscan_spi_bitstreams
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2 changes: 1 addition & 1 deletion third_party/edid-decode
Submodule edid-decode updated from dcc8b8 to b2da15
2 changes: 1 addition & 1 deletion third_party/liteusb
2 changes: 1 addition & 1 deletion third_party/litevideo
2 changes: 1 addition & 1 deletion third_party/litex
Submodule litex updated 61 files
+1 −0 .gitignore
+3 −0 .gitmodules
+25 −5 README
+150 −36 litex/boards/platforms/arty.py
+20 −11 litex/boards/platforms/arty_s7.py
+1 −1 litex/boards/platforms/de0nano.py
+120 −0 litex/boards/platforms/genesys2.py
+12 −6 litex/boards/platforms/kc705.py
+2 −4 litex/boards/targets/arty.py
+152 −0 litex/boards/targets/genesys2.py
+2 −2 litex/boards/targets/kc705.py
+18 −16 litex/boards/targets/nexys4ddr.py
+2 −4 litex/boards/targets/nexys_video.py
+1 −1 litex/build/altera/quartus.py
+4 −3 litex/build/generic_platform.py
+3 −2 litex/build/lattice/diamond.py
+1 −1 litex/build/lattice/icestorm.py
+6 −0 litex/build/sim/config.py
+15 −8 litex/build/sim/verilator.py
+1 −1 litex/build/xilinx/ise.py
+4 −0 litex/build/xilinx/platform.py
+12 −1 litex/build/xilinx/programmer.py
+14 −3 litex/build/xilinx/vivado.py
+0 −11 litex/gen/fhdl/verilog.py
+1 −1 litex/gen/sim/__init__.py
+2 −1 litex/gen/sim/core.py
+9 −4 litex/soc/cores/code_8b10b.py
+11 −3 litex/soc/cores/cpu/lm32/core.py
+0 −0 litex/soc/cores/cpu/lm32/verilog/config/lm32_config.v
+199 −0 litex/soc/cores/cpu/lm32/verilog/config_minimal/lm32_config.v
+6 −1 litex/soc/cores/cpu/mor1kx/core.py
+6 −1 litex/soc/cores/cpu/picorv32/core.py
+1 −0 litex/soc/cores/cpu/vexriscv/__init__.py
+154 −0 litex/soc/cores/cpu/vexriscv/core.py
+1 −0 litex/soc/cores/cpu/vexriscv/verilog
+25 −6 litex/soc/cores/uart.py
+7 −8 litex/soc/integration/builder.py
+24 −7 litex/soc/integration/cpu_interface.py
+0 −229 litex/soc/integration/sdram_init.py
+71 −21 litex/soc/integration/soc_core.py
+13 −22 litex/soc/integration/soc_sdram.py
+16 −0 litex/soc/interconnect/csr_bus.py
+23 −4 litex/soc/interconnect/wishbone.py
+8 −0 litex/soc/software/bios/Makefile
+1 −1 litex/soc/software/bios/boot-helper-picorv32.S
+4 −0 litex/soc/software/bios/boot-helper-vexriscv.S
+4 −0 litex/soc/software/bios/boot.c
+15 −3 litex/soc/software/bios/linker.ld
+28 −12 litex/soc/software/bios/main.c
+170 −49 litex/soc/software/bios/sdram.c
+11 −0 litex/soc/software/include/base/csr-defs.h
+22 −10 litex/soc/software/include/base/irq.h
+26 −0 litex/soc/software/include/base/system.h
+0 −0 litex/soc/software/libbase/crt0-picorv32.S
+76 −0 litex/soc/software/libbase/crt0-vexriscv.S
+24 −16 litex/soc/software/libbase/system.c
+36 −21 litex/soc/tools/litex_term.py
+7 −4 litex/soc/tools/mkmscimg.py
+22 −8 litex/soc/tools/remote/litex_server.py
+55 −0 litex_setup.py
+1 −1 setup.py

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