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Merge pull request #36 from ewenmcneill/update-submodules-2018-08-27
Update third party submodules (including edid-decode)
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Submodule edid-decode
updated
from dcc8b8 to b2da15
Submodule litedram
updated
24 files
+70 −39 | litedram/common.py | |
+47 −25 | litedram/core/bankmachine.py | |
+15 −7 | litedram/core/controller.py | |
+107 −6 | litedram/core/multiplexer.py | |
+81 −77 | litedram/frontend/adaptation.py | |
+245 −0 | litedram/frontend/axi.py | |
+165 −60 | litedram/frontend/bist.py | |
+56 −20 | litedram/frontend/crossbar.py | |
+58 −25 | litedram/frontend/dma.py | |
+3 −1 | litedram/frontend/wishbone.py | |
+222 −87 | litedram/modules.py | |
+5 −1 | litedram/phy/__init__.py | |
+0 −242 | litedram/phy/a7ddrphy.py | |
+0 −297 | litedram/phy/k7ddrphy.py | |
+17 −5 | litedram/phy/kusddrphy.py | |
+4 −1 | litedram/phy/s6ddrphy.py | |
+455 −0 | litedram/phy/s7ddrphy.py | |
+303 −0 | litedram/sdram_init.py | |
+1 −1 | setup.py | |
+150 −0 | test/test_axi.py | |
+3 −1 | test/test_bist.py | |
+5 −3 | test/test_bist_async.py | |
+5 −3 | test/test_downconverter.py | |
+5 −3 | test/test_upconverter.py |
Submodule liteeth
updated
10 files
+1 −1 | README | |
+1 −1 | liteeth/core/icmp.py | |
+817 −0 | liteeth/phy/a7_1000basex.py | |
+213 −0 | liteeth/phy/a7_gtp.py | |
+3 −3 | liteeth/phy/gmii.py | |
+3 −3 | liteeth/phy/gmii_mii.py | |
+2 −2 | liteeth/phy/mii.py | |
+345 −0 | liteeth/phy/pcs_1000basex.py | |
+0 −155 | liteeth/phy/s6rgmii.py | |
+1 −1 | setup.py |
Submodule litepcie
updated
14 files
+1 −1 | example_designs/make.py | |
+13 −10 | example_designs/test/test_regs.py | |
+24 −8 | litepcie/core/msi.py | |
+8 −9 | litepcie/core/tlp/depacketizer.py | |
+7 −5 | litepcie/core/tlp/packetizer.py | |
+2 −1 | litepcie/core/tlp/reordering.py | |
+11 −8 | litepcie/frontend/dma.py | |
+2 −2 | litepcie/frontend/wishbone.py | |
+9 −2 | litepcie/phy/s7pciephy.py | |
+2 −0 | litepcie/phy/xilinx/7-series/kintex7/pcie_core_top.v | |
+1 −1 | setup.py | |
+2 −1 | test/model/phy.py | |
+20 −13 | test/test_dma.py | |
+15 −6 | test/test_wishbone.py |
Submodule litesata
updated
5 files
+31 −0 | example_designs/platforms/genesys2.py | |
+7 −2 | example_designs/targets/bist.py | |
+10 −4 | example_designs/test/test_regs.py | |
+5 −4 | litesata/core/link.py | |
+1 −1 | setup.py |
Submodule litescope
updated
11 files
Submodule liteusb
updated
from 23d6a6 to e841c5
Submodule litevideo
updated
from 9b4169 to 7b4240
Submodule litex
updated
61 files
Submodule migen
updated
36 files