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TobyWR/README.md

Hi, I'm Toby!

I'm an Electronic Engineering student, with a passion for FPGA engineering and RTL design.

Technical Skills

Developing Proficiency

  • System Verilog / Verilog - RTL Design, FPGA Synthesis, Verification
  • C - Embedded software, AVR toolchain

Foundational Knowledge

  • C++
  • Python

Pinned Loading

  1. AXI4Lite-Peripheral AXI4Lite-Peripheral Public

    A Simple Counter peripheral designed in System verilog and C++, utilizing AXI4 Lite.

    SystemVerilog

  2. RISCV32I RISCV32I Public

    Simple RISC-V 32 I Single cycle processor designed in SystemVerilog. 32-Bit datapath, with 32 general purpose registers.

    SystemVerilog

  3. UDP-Packet-Parser UDP-Packet-Parser Public

    Simple pipelined UDP Packet Parser designed in System Verilog.

    SystemVerilog