[FCCM 2019] Hardware Acceleration of Long Read Pairwise Overlapping in Genome Sequencing: A Race Between FPGA and GPU
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Updated
Jul 23, 2019 - C
[FCCM 2019] Hardware Acceleration of Long Read Pairwise Overlapping in Genome Sequencing: A Race Between FPGA and GPU
The purpose of this project was to design an accelarator using C and design tools from Xilinx, like the Vivado High level Synthesis for the inner design of the Accelarator and the SDSoC to design the transfer of the data in Zynq-7000.
This version of crispy-DOOM uses 8 HW accelerators on the FPGA
Example program demonstrating the use of the Revere-AMU System Architecture from userspace, with VFIO
POWER9 gzip engine documentation and code samples
Short exercises for GPU at Complutense University of Madrid. Mirror from GitLab
SmartTLS is the project introduced at the paper "A Case for SmartNIC-accelerated Private Communication" (APNET 20). It accelerates web servers by offloading TLS handshake protocol into network card (NIC).
68000 Relocator with FLASH Kickstart
FPGA-based accelerator for compactions in LSM-tree based KV stores. Making compaction great again, again!
Deploying_CNN_on_DE10nano_using_OpenCL
A benchmarking suite for heterogeneous systems. The primary goal of this project is to improve and update aspects of existing benchmarking suites which are either insufficient or outdated.
A lightweight well-featured CLI downloader optimized for speed and early preview.
Accelerator for Hyperdimensional Computing (HDC)
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