A simple and scaleable Self Organizing Map implementation written in VHDL. Tested on ARTYA7-35T board.
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Updated
Jan 31, 2021 - VHDL
A simple and scaleable Self Organizing Map implementation written in VHDL. Tested on ARTYA7-35T board.
Personal FPGA Proyects mostly Xilinx / Vivado and Some Multisim
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