This contains my solution to the labs of Computer Architecture course for the year 2020-21
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Updated
Dec 14, 2020 - Verilog
This contains my solution to the labs of Computer Architecture course for the year 2020-21
This is a ModelSim project that implements a MIPS pipelined CPU using Verilog. This project builds upon the concepts from the single-cycle CPU to create a more efficient CPU by using pipelining.
This is a ModelSim project that implements a MIPS single-cycle CPU using Verilog.
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